Re: [PATCH 11/11] clocksource: new RISC-V SBI timer driver

2018-08-03 Thread Christoph Hellwig
>> +/* >> + * It is guarnteed that all the timers across all the harts are synchronized > > /s/guarnteed/guaranteed Fixed.

Re: [PATCH 11/11] clocksource: new RISC-V SBI timer driver

2018-08-03 Thread Christoph Hellwig
>> +/* >> + * It is guarnteed that all the timers across all the harts are synchronized > > /s/guarnteed/guaranteed Fixed.

Re: [PATCH 11/11] clocksource: new RISC-V SBI timer driver

2018-08-02 Thread Atish Patra
On 8/2/18 4:51 AM, Christoph Hellwig wrote: From: Palmer Dabbelt The RISC-V ISA defines a per-hart real-time clock and timer, which is present on all systems. The clock is accessed via the 'rdtime' pseudo-instruction (which reads a CSR), and the timer is set via an SBI call. Contains various

Re: [PATCH 11/11] clocksource: new RISC-V SBI timer driver

2018-08-02 Thread Atish Patra
On 8/2/18 4:51 AM, Christoph Hellwig wrote: From: Palmer Dabbelt The RISC-V ISA defines a per-hart real-time clock and timer, which is present on all systems. The clock is accessed via the 'rdtime' pseudo-instruction (which reads a CSR), and the timer is set via an SBI call. Contains various

[PATCH 11/11] clocksource: new RISC-V SBI timer driver

2018-08-02 Thread Christoph Hellwig
From: Palmer Dabbelt The RISC-V ISA defines a per-hart real-time clock and timer, which is present on all systems. The clock is accessed via the 'rdtime' pseudo-instruction (which reads a CSR), and the timer is set via an SBI call. Contains various improvements from Atish Patra .

[PATCH 11/11] clocksource: new RISC-V SBI timer driver

2018-08-02 Thread Christoph Hellwig
From: Palmer Dabbelt The RISC-V ISA defines a per-hart real-time clock and timer, which is present on all systems. The clock is accessed via the 'rdtime' pseudo-instruction (which reads a CSR), and the timer is set via an SBI call. Contains various improvements from Atish Patra .