On 16/09/16 15:14, Stanimir Varbanov wrote:
> + writel_relaxed(0x0f, base + QSERDES_COM_BG_TRIM);
> + writel_relaxed(0x0f, base + QSERDES_COM_PLL_IVCO);
> + writel_relaxed(0x19, base + QSERDES_COM_CLK_EP_DIV);
> + writel_relaxed(0x10, base + QSERDES_COM_CLK_ENABLE1);
> +
On 16/09/16 15:14, Stanimir Varbanov wrote:
> + writel_relaxed(0x0f, base + QSERDES_COM_BG_TRIM);
> + writel_relaxed(0x0f, base + QSERDES_COM_PLL_IVCO);
> + writel_relaxed(0x19, base + QSERDES_COM_CLK_EP_DIV);
> + writel_relaxed(0x10, base + QSERDES_COM_CLK_ENABLE1);
> +
On 13/09/16 17:06, Archit Taneja wrote:
On 9/7/2016 4:25 PM, Srinivas Kandagatla wrote:
This patch adds support to msm8996 pcie phy which supports 3 ports,
Port A, Port B and Port C.
Each port is independent and connected to a pcie host controller,
there is
also a common block which is
On 13/09/16 17:06, Archit Taneja wrote:
On 9/7/2016 4:25 PM, Srinivas Kandagatla wrote:
This patch adds support to msm8996 pcie phy which supports 3 ports,
Port A, Port B and Port C.
Each port is independent and connected to a pcie host controller,
there is
also a common block which is
Hi Srini,
> +
> +static int qcom_msm8996_phy_common_power_off(struct phy *phy)
> +{
> + struct phy_msm8996_desc *phydesc = phy_get_drvdata(phy);
> + struct phy_msm8996_priv *priv = phydesc->priv;
> + void __iomem *base = priv->base;
> +
> + mutex_lock(>phy_mutex);
> + if
Hi Srini,
> +
> +static int qcom_msm8996_phy_common_power_off(struct phy *phy)
> +{
> + struct phy_msm8996_desc *phydesc = phy_get_drvdata(phy);
> + struct phy_msm8996_priv *priv = phydesc->priv;
> + void __iomem *base = priv->base;
> +
> + mutex_lock(>phy_mutex);
> + if
On 9/7/2016 4:25 PM, Srinivas Kandagatla wrote:
This patch adds support to msm8996 pcie phy which supports 3 ports,
Port A, Port B and Port C.
Each port is independent and connected to a pcie host controller, there is
also a common block which is shared across all the 3 ports.
Signed-off-by:
On 9/7/2016 4:25 PM, Srinivas Kandagatla wrote:
This patch adds support to msm8996 pcie phy which supports 3 ports,
Port A, Port B and Port C.
Each port is independent and connected to a pcie host controller, there is
also a common block which is shared across all the 3 ports.
Signed-off-by:
This patch adds support to msm8996 pcie phy which supports 3 ports,
Port A, Port B and Port C.
Each port is independent and connected to a pcie host controller, there is
also a common block which is shared across all the 3 ports.
Signed-off-by: Srinivas Kandagatla
This patch adds support to msm8996 pcie phy which supports 3 ports,
Port A, Port B and Port C.
Each port is independent and connected to a pcie host controller, there is
also a common block which is shared across all the 3 ports.
Signed-off-by: Srinivas Kandagatla
---
drivers/phy/Kconfig
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