On Tue, Aug 16, 2016 at 8:06 AM, Icenowy Zheng wrote:
>
>
> 15.08.2016, 21:56, "Chen-Yu Tsai" :
>> Hi,
>>
>> On Mon, Aug 1, 2016 at 10:59 PM, Icenowy Zheng wrote:
>>> The A64 has a R_PIO pin controller, similar to the one found on the H3
>>> SoCs.
>>> Add support for the pins controlled by the R_PIO controller.
>>>
>>> Signed-off-by: Icenowy Zheng
>>> ---
>>> drivers/pinctrl/sunxi/Kconfig | 5 +
>>> drivers/pinctrl/sunxi/Makefile | 1 +
>>> drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c | 148
>>> +++
>>> 3 files changed, 154 insertions(+)
>>> create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c
>>>
>>> diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
>>> index aaf075b..c4b476f 100644
>>> --- a/drivers/pinctrl/sunxi/Kconfig
>>> +++ b/drivers/pinctrl/sunxi/Kconfig
>>> @@ -72,4 +72,9 @@ config PINCTRL_SUN50I_A64
>>> bool
>>> select PINCTRL_SUNXI
>>>
>>> +config PINCTRL_SUN50I_A64_R
>>> + bool
>>> + depends on RESET_CONTROLLER
>>> + select PINCTRL_SUNXI
>>> +
>>> endif
>>> diff --git a/drivers/pinctrl/sunxi/Makefile
>>> b/drivers/pinctrl/sunxi/Makefile
>>> index 2d8b64e..d6eabdd 100644
>>> --- a/drivers/pinctrl/sunxi/Makefile
>>> +++ b/drivers/pinctrl/sunxi/Makefile
>>> @@ -13,6 +13,7 @@ obj-$(CONFIG_PINCTRL_SUN8I_A23) += pinctrl-sun8i-a23.o
>>> obj-$(CONFIG_PINCTRL_SUN8I_A23_R) += pinctrl-sun8i-a23-r.o
>>> obj-$(CONFIG_PINCTRL_SUN8I_A33) += pinctrl-sun8i-a33.o
>>> obj-$(CONFIG_PINCTRL_SUN50I_A64) += pinctrl-sun50i-a64.o
>>> +obj-$(CONFIG_PINCTRL_SUN50I_A64_R) += pinctrl-sun50i-a64-r.o
>>> obj-$(CONFIG_PINCTRL_SUN8I_A83T) += pinctrl-sun8i-a83t.o
>>> obj-$(CONFIG_PINCTRL_SUN8I_H3) += pinctrl-sun8i-h3.o
>>> obj-$(CONFIG_PINCTRL_SUN8I_H3_R) += pinctrl-sun8i-h3-r.o
>>> diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c
>>> b/drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c
>>> new file mode 100644
>>> index 000..b836264
>>> --- /dev/null
>>> +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c
>>> @@ -0,0 +1,148 @@
>>> +/*
>>> + * Allwinner A64 SoCs special pins pinctrl driver.
>>> + *
>>> + * Based on pinctrl-sun8i-a23-r.c
>>> + *
>>> + * Copyright (C) 2016 Icenowy Zheng
>>> + * Icenowy Zheng
>>> + *
>>> + * Copyright (C) 2014 Chen-Yu Tsai
>>> + * Chen-Yu Tsai
>>> + *
>>> + * Copyright (C) 2014 Boris Brezillon
>>> + * Boris Brezillon
>>> + *
>>> + * Copyright (C) 2014 Maxime Ripard
>>> + * Maxime Ripard
>>> + *
>>> + * This file is licensed under the terms of the GNU General Public
>>> + * License version 2. This program is licensed "as is" without any
>>> + * warranty of any kind, whether express or implied.
>>> + */
>>> +
>>> +#include
>>> +#include
>>> +#include
>>> +#include
>>
>> Please sort the headers.
> This file is based on pinctrl-sun8i-a23-r.c and pinctrl-sun8i-h3-r.c, which
> both have #include in this sequence.
And we should probably fix them too.
>>
>>> +#include
>>> +#include
>>> +
>>> +#include "pinctrl-sunxi.h"
>>> +
>>> +static const struct sunxi_desc_pin sun50i_a64_r_pins[] = {
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "s_rsb"), /* SCK */
>>> + SUNXI_FUNCTION(0x3, "s_twi"), /* SCK */
>>
>> We use "i2c" instead of "twi".
> So as above, in A23 / H3 R_PIO driver, they're called as "s_twi" other than
> "s_i2c"
These as well.
ChenYu
>>
>>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PL_EINT0 */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "s_rsb"), /* SDA */
>>> + SUNXI_FUNCTION(0x3, "s_twi"), /* SDA */
>>
>> Same here.
>>
>>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PL_EINT1 */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "s_uart"), /* TX */
>>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PL_EINT2 */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "s_uart"), /* RX */
>>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PL_EINT3 */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x3, "s_jtag"), /* MS */
>>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PL_EINT4 */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x3, "s_jtag"), /* CK */
>>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PL_EINT5 */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x3, "s_jtag"), /* DO */
>>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PL_EINT6 */
>>> + SUNXI_PIN(S
