Re: [PATCH 2/2] x86/MCE/AMD Support new memory interleaving schemes during address translation

On Sat, Aug 15, 2020 at 11:13:36AM +0200, Ingo Molnar wrote: > > * Yazen Ghannam wrote: > > > + /* Read D18F1x208 (System Fabric ID Mask 0). */ > > + if (amd_df_indirect_read(nid, 1, 0x208, umc, )) > > + goto out_err; > > + > > + /* Determine if system is a legacy Data

Re: [PATCH 2/2] x86/MCE/AMD Support new memory interleaving schemes during address translation

* Yazen Ghannam wrote: > + /* Read D18F1x208 (System Fabric ID Mask 0). */ > + if (amd_df_indirect_read(nid, 1, 0x208, umc, )) > + goto out_err; > + > + /* Determine if system is a legacy Data Fabric type. */ > + legacy_df = !(tmp & 0xFF); 1) I see this pattern in

[PATCH 2/2] x86/MCE/AMD Support new memory interleaving schemes during address translation

From: Muralidhara M K Add support for new memory interleaving schemes used in current AMD systems. Check if the system is using a current Data Fabric version or a legacy version as some bit and register definitions have changed. Tested on AMD reference platforms with the following memory