Re: [PATCH 2/3] phy: exynos-mipi-video: Rewrite handling of phy registers

On 03/23/2016 12:09 PM, Marek Szyprowski wrote: > Controlling Exynos MIPI DPHY is done by handling 2 registers: one for > phy reset and one for enabling it. This patch moves definitions of those > 2 registers to speparate exynos_mipi_phy_desc structure, which can be > defined separately for each

Re: [PATCH 2/3] phy: exynos-mipi-video: Rewrite handling of phy registers

On 03/23/2016 12:09 PM, Marek Szyprowski wrote: > Controlling Exynos MIPI DPHY is done by handling 2 registers: one for > phy reset and one for enabling it. This patch moves definitions of those > 2 registers to speparate exynos_mipi_phy_desc structure, which can be > defined separately for each

[PATCH 2/3] phy: exynos-mipi-video: Rewrite handling of phy registers

Controlling Exynos MIPI DPHY is done by handling 2 registers: one for phy reset and one for enabling it. This patch moves definitions of those 2 registers to speparate exynos_mipi_phy_desc structure, which can be defined separately for each PHY for each supported hardware variant. This code

[PATCH 2/3] phy: exynos-mipi-video: Rewrite handling of phy registers

Controlling Exynos MIPI DPHY is done by handling 2 registers: one for phy reset and one for enabling it. This patch moves definitions of those 2 registers to speparate exynos_mipi_phy_desc structure, which can be defined separately for each PHY for each supported hardware variant. This code