On Tue, 2015-10-27 at 19:30 -0700, Nishanth Aravamudan wrote:
> On 28.10.2015 [11:20:05 +0900], Benjamin Herrenschmidt wrote:
> > On Tue, 2015-10-27 at 18:54 -0700, Nishanth Aravamudan wrote:
> > >
> > > In "bypass" mode, what TCE size is used? Is it guaranteed to be
> > > 4K?
> >
> > None :-)
On 28.10.2015 [11:20:05 +0900], Benjamin Herrenschmidt wrote:
> On Tue, 2015-10-27 at 18:54 -0700, Nishanth Aravamudan wrote:
> >
> > In "bypass" mode, what TCE size is used? Is it guaranteed to be 4K?
>
> None :-) The TCEs are completely bypassed. You get a N:M linear mapping
> of all memory
On Tue, 2015-10-27 at 18:54 -0700, Nishanth Aravamudan wrote:
>
> In "bypass" mode, what TCE size is used? Is it guaranteed to be 4K?
None :-) The TCEs are completely bypassed. You get a N:M linear mapping
of all memory starting at 1<<59 PCI side.
> Seems like this would be a different platform
On 28.10.2015 [12:00:20 +1100], Alexey Kardashevskiy wrote:
> On 10/28/2015 09:27 AM, Nishanth Aravamudan wrote:
> >On 27.10.2015 [17:02:16 +1100], Alexey Kardashevskiy wrote:
> >>On 10/24/2015 07:57 AM, Nishanth Aravamudan wrote:
> >>>On Power, the kernel's page size can differ from the IOMMU's
On 10/28/2015 09:27 AM, Nishanth Aravamudan wrote:
On 27.10.2015 [17:02:16 +1100], Alexey Kardashevskiy wrote:
On 10/24/2015 07:57 AM, Nishanth Aravamudan wrote:
On Power, the kernel's page size can differ from the IOMMU's page size,
so we need to override the generic implementation, which
On 27.10.2015 [17:02:16 +1100], Alexey Kardashevskiy wrote:
> On 10/24/2015 07:57 AM, Nishanth Aravamudan wrote:
> >On Power, the kernel's page size can differ from the IOMMU's page size,
> >so we need to override the generic implementation, which always returns
> >the kernel's page size. Lookup
On Tue, Oct 27, 2015 at 05:02:16PM +1100, Alexey Kardashevskiy wrote:
> >+unsigned long dma_get_page_shift(struct device *dev)
> >+{
> >+struct iommu_table *tbl = get_iommu_table_base(dev);
> >+if (tbl)
> >+return tbl->it_page_shift;
>
>
> All PCI devices have this
On 10/24/2015 07:57 AM, Nishanth Aravamudan wrote:
On Power, the kernel's page size can differ from the IOMMU's page size,
so we need to override the generic implementation, which always returns
the kernel's page size. Lookup the IOMMU's page size from struct
iommu_table, if available. Fallback
On 10/24/2015 07:57 AM, Nishanth Aravamudan wrote:
On Power, the kernel's page size can differ from the IOMMU's page size,
so we need to override the generic implementation, which always returns
the kernel's page size. Lookup the IOMMU's page size from struct
iommu_table, if available. Fallback
On 27.10.2015 [17:02:16 +1100], Alexey Kardashevskiy wrote:
> On 10/24/2015 07:57 AM, Nishanth Aravamudan wrote:
> >On Power, the kernel's page size can differ from the IOMMU's page size,
> >so we need to override the generic implementation, which always returns
> >the kernel's page size. Lookup
On 28.10.2015 [12:00:20 +1100], Alexey Kardashevskiy wrote:
> On 10/28/2015 09:27 AM, Nishanth Aravamudan wrote:
> >On 27.10.2015 [17:02:16 +1100], Alexey Kardashevskiy wrote:
> >>On 10/24/2015 07:57 AM, Nishanth Aravamudan wrote:
> >>>On Power, the kernel's page size can differ from the IOMMU's
On 10/28/2015 09:27 AM, Nishanth Aravamudan wrote:
On 27.10.2015 [17:02:16 +1100], Alexey Kardashevskiy wrote:
On 10/24/2015 07:57 AM, Nishanth Aravamudan wrote:
On Power, the kernel's page size can differ from the IOMMU's page size,
so we need to override the generic implementation, which
On Tue, 2015-10-27 at 18:54 -0700, Nishanth Aravamudan wrote:
>
> In "bypass" mode, what TCE size is used? Is it guaranteed to be 4K?
None :-) The TCEs are completely bypassed. You get a N:M linear mapping
of all memory starting at 1<<59 PCI side.
> Seems like this would be a different platform
On 28.10.2015 [11:20:05 +0900], Benjamin Herrenschmidt wrote:
> On Tue, 2015-10-27 at 18:54 -0700, Nishanth Aravamudan wrote:
> >
> > In "bypass" mode, what TCE size is used? Is it guaranteed to be 4K?
>
> None :-) The TCEs are completely bypassed. You get a N:M linear mapping
> of all memory
On Tue, 2015-10-27 at 19:30 -0700, Nishanth Aravamudan wrote:
> On 28.10.2015 [11:20:05 +0900], Benjamin Herrenschmidt wrote:
> > On Tue, 2015-10-27 at 18:54 -0700, Nishanth Aravamudan wrote:
> > >
> > > In "bypass" mode, what TCE size is used? Is it guaranteed to be
> > > 4K?
> >
> > None :-)
On Tue, Oct 27, 2015 at 05:02:16PM +1100, Alexey Kardashevskiy wrote:
> >+unsigned long dma_get_page_shift(struct device *dev)
> >+{
> >+struct iommu_table *tbl = get_iommu_table_base(dev);
> >+if (tbl)
> >+return tbl->it_page_shift;
>
>
> All PCI devices have this
On Power, the kernel's page size can differ from the IOMMU's page size,
so we need to override the generic implementation, which always returns
the kernel's page size. Lookup the IOMMU's page size from struct
iommu_table, if available. Fallback to the kernel's page size,
otherwise.
Signed-off-by:
On Power, the kernel's page size can differ from the IOMMU's page size,
so we need to override the generic implementation, which always returns
the kernel's page size. Lookup the IOMMU's page size from struct
iommu_table, if available. Fallback to the kernel's page size,
otherwise.
Signed-off-by:
18 matches
Mail list logo
