Re: [PATCH 4/4] clk: mediatek: Add MT6797 clock support

[Matthias Brugger]

On 09/08/2016 12:49 PM, Mars Cheng wrote:

Add MT6797 clock support, include topckgen, apmixedsys,
infracfg and subsystem clocks.

Signed-off-by: Mars Cheng 
---
 arch/arm64/boot/dts/mediatek/mt6797.dtsi |   66 ++-
 drivers/clk/mediatek/Kconfig |   36 ++
 drivers/clk/mediatek/Makefile|5 +
 drivers/clk/mediatek/clk-mt6797-img.c|   87 
 drivers/clk/mediatek/clk-mt6797-mm.c |  146 ++
 drivers/clk/mediatek/clk-mt6797-vdec.c   |  102 +
 drivers/clk/mediatek/clk-mt6797-venc.c   |   86 
 drivers/clk/mediatek/clk-mt6797.c|  716 ++
 include/dt-bindings/clock/mt6797-clk.h   |  281 
 9 files changed, 1514 insertions(+), 11 deletions(-)
 create mode 100644 drivers/clk/mediatek/clk-mt6797-img.c
 create mode 100644 drivers/clk/mediatek/clk-mt6797-mm.c
 create mode 100644 drivers/clk/mediatek/clk-mt6797-vdec.c
 create mode 100644 drivers/clk/mediatek/clk-mt6797-venc.c
 create mode 100644 drivers/clk/mediatek/clk-mt6797.c
 create mode 100644 include/dt-bindings/clock/mt6797-clk.h

diff --git a/arch/arm64/boot/dts/mediatek/mt6797.dtsi 
b/arch/arm64/boot/dts/mediatek/mt6797.dtsi
index 66f6442..75d3877 100644
--- a/arch/arm64/boot/dts/mediatek/mt6797.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt6797.dtsi
@@ -10,6 +10,7 @@
  * GNU General Public License for more details.
  */

+#include 
 #include 
 #include 

@@ -113,12 +114,6 @@
clock-output-names = "clk32k";
};

-   uart_clk: dummy26m {
-   compatible = "fixed-clock";
-   clock-frequency = <2600>;
-   #clock-cells = <0>;
-   };
-
timer {
compatible = "arm,armv8-timer";
interrupt-parent = <>;
@@ -132,6 +127,24 @@
 (GIC_CPU_MASK_SIMPLE(10) | IRQ_TYPE_LEVEL_LOW)>;
};

+   topckgen: topckgen@1000 {
+   compatible = "mediatek,mt6797-topckgen";
+   reg = <0 0x1000 0 0x1000>;
+   #clock-cells = <1>;
+   };
+
+   infrasys: infracfg_ao@10001000 {
+   compatible = "mediatek,mt6797-infracfg", "syscon";
+   reg = <0 0x10001000 0 0x1000>;
+   #clock-cells = <1>;
+   };
+
+   apmixedsys: apmixed@1000c000 {
+   compatible = "mediatek,mt6797-apmixedsys";
+   reg = <0 0x1000c000 0 0x1000>;
+   #clock-cells = <1>;
+   };
+
sysirq: intpol-controller@10200620 {
compatible = "mediatek,mt6797-sysirq",
 "mediatek,mt6577-sysirq";
@@ -148,7 +161,9 @@
 "mediatek,mt6577-uart";
reg = <0 0x11002000 0 0x400>;
interrupts = ;
-   clocks = <_clk>;
+   clocks = < CLK_INFRA_UART0>,
+< CLK_INFRA_AP_DMA>;
+   clock-names = "baud", "bus";
status = "disabled";
};

@@ -157,7 +172,9 @@
 "mediatek,mt6577-uart";
reg = <0 0x11003000 0 0x400>;
interrupts = ;
-   clocks = <_clk>;
+   clocks = < CLK_INFRA_UART1>,
+< CLK_INFRA_AP_DMA>;
+   clock-names = "baud", "bus";
status = "disabled";
};

@@ -166,7 +183,9 @@
 "mediatek,mt6577-uart";
reg = <0 0x11004000 0 0x400>;
interrupts = ;
-   clocks = <_clk>;
+   clocks = < CLK_INFRA_UART2>,
+< CLK_INFRA_AP_DMA>;
+   clock-names = "baud", "bus";
status = "disabled";
};

@@ -175,10 +194,36 @@
 "mediatek,mt6577-uart";
reg = <0 0x11005000 0 0x400>;
interrupts = ;
-   clocks = <_clk>;
+   clocks = < CLK_INFRA_UART3>,
+< CLK_INFRA_AP_DMA>;
+   clock-names = "baud", "bus";
status = "disabled";
};

+   mmsys: mmsys_config@1400 {
+   compatible = "mediatek,mt6797-mmsys", "syscon";
+   reg = <0 0x1400 0 0x1000>;
+   #clock-cells = <1>;
+   };
+
+   imgsys: imgsys_config@1500  {
+   compatible = "mediatek,mt6797-imgsys", "syscon";
+   reg = <0 0x1500 0 0x1000>;
+   #clock-cells = <1>;
+   };
+
+   vdecsys: vdec_gcon@1600 {
+   compatible = "mediatek,mt6797-vdecsys", "syscon";
+   reg = <0 0x1600 0 0x1>;
+   #clock-cells = <1>;
+   };
+
+   vencsys: venc_gcon@1700 {
+   compatible = "mediatek,mt6797-vencsys", "syscon";
+   reg = <0 0x1700 0 0x1000>;
+   #clock-cells = <1>;
+   };
+
gic: interrupt-controller@1900 {
compatible = 

Re: [PATCH 4/4] clk: mediatek: Add MT6797 clock support

[Matthias Brugger]

On 09/08/2016 12:49 PM, Mars Cheng wrote:

Add MT6797 clock support, include topckgen, apmixedsys,
infracfg and subsystem clocks.

Signed-off-by: Mars Cheng 
---
 arch/arm64/boot/dts/mediatek/mt6797.dtsi |   66 ++-
 drivers/clk/mediatek/Kconfig |   36 ++
 drivers/clk/mediatek/Makefile|5 +
 drivers/clk/mediatek/clk-mt6797-img.c|   87 
 drivers/clk/mediatek/clk-mt6797-mm.c |  146 ++
 drivers/clk/mediatek/clk-mt6797-vdec.c   |  102 +
 drivers/clk/mediatek/clk-mt6797-venc.c   |   86 
 drivers/clk/mediatek/clk-mt6797.c|  716 ++
 include/dt-bindings/clock/mt6797-clk.h   |  281 
 9 files changed, 1514 insertions(+), 11 deletions(-)
 create mode 100644 drivers/clk/mediatek/clk-mt6797-img.c
 create mode 100644 drivers/clk/mediatek/clk-mt6797-mm.c
 create mode 100644 drivers/clk/mediatek/clk-mt6797-vdec.c
 create mode 100644 drivers/clk/mediatek/clk-mt6797-venc.c
 create mode 100644 drivers/clk/mediatek/clk-mt6797.c
 create mode 100644 include/dt-bindings/clock/mt6797-clk.h

diff --git a/arch/arm64/boot/dts/mediatek/mt6797.dtsi 
b/arch/arm64/boot/dts/mediatek/mt6797.dtsi
index 66f6442..75d3877 100644
--- a/arch/arm64/boot/dts/mediatek/mt6797.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt6797.dtsi
@@ -10,6 +10,7 @@
  * GNU General Public License for more details.
  */

+#include 
 #include 
 #include 

@@ -113,12 +114,6 @@
clock-output-names = "clk32k";
};

-   uart_clk: dummy26m {
-   compatible = "fixed-clock";
-   clock-frequency = <2600>;
-   #clock-cells = <0>;
-   };
-
timer {
compatible = "arm,armv8-timer";
interrupt-parent = <>;
@@ -132,6 +127,24 @@
 (GIC_CPU_MASK_SIMPLE(10) | IRQ_TYPE_LEVEL_LOW)>;
};

+   topckgen: topckgen@1000 {
+   compatible = "mediatek,mt6797-topckgen";
+   reg = <0 0x1000 0 0x1000>;
+   #clock-cells = <1>;
+   };
+
+   infrasys: infracfg_ao@10001000 {
+   compatible = "mediatek,mt6797-infracfg", "syscon";
+   reg = <0 0x10001000 0 0x1000>;
+   #clock-cells = <1>;
+   };
+
+   apmixedsys: apmixed@1000c000 {
+   compatible = "mediatek,mt6797-apmixedsys";
+   reg = <0 0x1000c000 0 0x1000>;
+   #clock-cells = <1>;
+   };
+
sysirq: intpol-controller@10200620 {
compatible = "mediatek,mt6797-sysirq",
 "mediatek,mt6577-sysirq";
@@ -148,7 +161,9 @@
 "mediatek,mt6577-uart";
reg = <0 0x11002000 0 0x400>;
interrupts = ;
-   clocks = <_clk>;
+   clocks = < CLK_INFRA_UART0>,
+< CLK_INFRA_AP_DMA>;
+   clock-names = "baud", "bus";
status = "disabled";
};

@@ -157,7 +172,9 @@
 "mediatek,mt6577-uart";
reg = <0 0x11003000 0 0x400>;
interrupts = ;
-   clocks = <_clk>;
+   clocks = < CLK_INFRA_UART1>,
+< CLK_INFRA_AP_DMA>;
+   clock-names = "baud", "bus";
status = "disabled";
};

@@ -166,7 +183,9 @@
 "mediatek,mt6577-uart";
reg = <0 0x11004000 0 0x400>;
interrupts = ;
-   clocks = <_clk>;
+   clocks = < CLK_INFRA_UART2>,
+< CLK_INFRA_AP_DMA>;
+   clock-names = "baud", "bus";
status = "disabled";
};

@@ -175,10 +194,36 @@
 "mediatek,mt6577-uart";
reg = <0 0x11005000 0 0x400>;
interrupts = ;
-   clocks = <_clk>;
+   clocks = < CLK_INFRA_UART3>,
+< CLK_INFRA_AP_DMA>;
+   clock-names = "baud", "bus";
status = "disabled";
};

+   mmsys: mmsys_config@1400 {
+   compatible = "mediatek,mt6797-mmsys", "syscon";
+   reg = <0 0x1400 0 0x1000>;
+   #clock-cells = <1>;
+   };
+
+   imgsys: imgsys_config@1500  {
+   compatible = "mediatek,mt6797-imgsys", "syscon";
+   reg = <0 0x1500 0 0x1000>;
+   #clock-cells = <1>;
+   };
+
+   vdecsys: vdec_gcon@1600 {
+   compatible = "mediatek,mt6797-vdecsys", "syscon";
+   reg = <0 0x1600 0 0x1>;
+   #clock-cells = <1>;
+   };
+
+   vencsys: venc_gcon@1700 {
+   compatible = "mediatek,mt6797-vencsys", "syscon";
+   reg = <0 0x1700 0 0x1000>;
+   #clock-cells = <1>;
+   };
+
gic: interrupt-controller@1900 {
compatible = "arm,gic-v3";

Re: [PATCH 4/4] clk: mediatek: Add MT6797 clock support

[Mars Cheng]

Hi Stephen

Thanks for your review. Response inlined.

On Thu, 2016-09-08 at 12:50 -0700, Stephen Boyd wrote:
> On 09/08/2016 03:49 AM, Mars Cheng wrote:
> > Add MT6797 clock support, include topckgen, apmixedsys,
> > infracfg and subsystem clocks.
> >
> > Signed-off-by: Mars Cheng 
> > ---
> >  arch/arm64/boot/dts/mediatek/mt6797.dtsi |   66 ++-
> 
> Please don't combine dts and clk driver changes together. We generally
> don't take dts changes through clk tree.

OK, will separate clk driver in single submit next time.

> 
> > diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
> > index 5aa6204..ce91ecb 100644
> > --- a/drivers/clk/mediatek/Kconfig
> > +++ b/drivers/clk/mediatek/Kconfig
> > @@ -56,6 +56,42 @@ config COMMON_CLK_MT2701_BDPSYS
> > ---help---
> >   This driver supports Mediatek MT2701 bdpsys clocks.
> >  
> 
> What tree is this based on?
Also 4.8-rc1, will base on clk-next to sent the patch.

> 
> > +config COMMON_CLK_MT6797
> > +   bool "Clock driver for Mediatek MT6797"
> > +   depends on COMMON_CLK
> 
> This sort of depends shouldn't be necessary.
> 

Got it. Will fix like this:
+config COMMON_CLK_MT6797
+   bool "Clock driver for Mediatek MT6797"
+   select COMMON_CLK_MEDIATEK
+   default ARCH_MEDIATEK
+   ---help---
+ This driver supports Mediatek MT6797 basic clocks.

> > +   select COMMON_CLK_MEDIATEK
> > +   default ARCH_MEDIATEK
> > +   ---help---
> > + This driver supports Mediatek MT6797 basic clocks.
> > +
> >
> >
> > diff --git a/drivers/clk/mediatek/clk-mt6797-img.c 
> > b/drivers/clk/mediatek/clk-mt6797-img.c
> > new file mode 100644
> > index 000..4ecd201
> > --- /dev/null
> > +++ b/drivers/clk/mediatek/clk-mt6797-img.c
> > @@ -0,0 +1,87 @@
> > +/* Copyright (c) 2016 MediaTek Inc.
> > + * Author: Kevin Chen 
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License version 2 as
> > + * published by the Free Software Foundation.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#include 
> 
> clk-provider.h?

Sure. Will fix it.

> 
> > +#include 
> > +#include 
> > +
> > +#include "clk-mtk.h"
> > +#include "clk-gate.h"
> > +
> > +static const struct mtk_gate_regs img_cg_regs = {
> > +   .set_ofs = 0x0004,
> > +   .clr_ofs = 0x0008,
> > +   .sta_ofs = 0x,
> > +};
> > +
> > +#define GATE_IMG(_id, _name, _parent, _shift) {\
> > +   .id = _id,  \
> > +   .name = _name,  \
> > +   .parent_name = _parent, \
> > +   .regs = _cg_regs,   \
> > +   .shift = _shift,\
> > +   .ops = _clk_gate_ops_setclr,\
> > +   }
> > +
> > +static const struct mtk_gate img_clks[] = {
> > +   GATE_IMG(CLK_IMG_FDVT, "img_fdvt", "mm_sel", 11),
> > +   GATE_IMG(CLK_IMG_DPE, "img_dpe", "mm_sel", 10),
> > +   GATE_IMG(CLK_IMG_DIP, "img_dip", "mm_sel", 6),
> > +   GATE_IMG(CLK_IMG_LARB6, "img_larb6", "mm_sel", 0),
> > +};
> > +
> > +static int mtk_imgsys_init(struct device *dev)
> > +{
> > +   struct clk_onecell_data *clk_data;
> > +   int r;
> > +
> > +   clk_data = mtk_alloc_clk_data(CLK_IMG_NR);
> > +   if (!clk_data) {
> > +   pr_err("%s: alloc failed\n", __func__);
> 
> Allocations already print a big error message so this is useless.

OK, will just return error code.

> 
> > +   goto alloc_err;
> > +   }
> > +
> > +   mtk_clk_register_gates(dev->of_node, img_clks, ARRAY_SIZE(img_clks),
> > +  clk_data);
> > +
> > +   r = of_clk_add_provider(dev->of_node, of_clk_src_onecell_get,
> > +   clk_data);
> > +   if (r)
> > +   pr_err("%s: could not register clock provider: %d\n",
> > +  __func__, r);
> > +
> > +   return r;
> > +
> > +alloc_err:
> > +   return -ENOMEM;
> > +}
> > +
> > +static const struct of_device_id of_match_clk_mt6797_img[] = {
> > +   { .compatible = "mediatek,mt6797-imgsys", },
> > +   {}
> > +};
> > +
> > +static int clk_mt6797_img_probe(struct platform_device *pdev)
> > +{
> > +   return mtk_imgsys_init(>dev);
> > +}
> > +
> > +static struct platform_driver clk_mt6797_img_drv = {
> > +   .probe = clk_mt6797_img_probe,
> > +   .driver = {
> > +   .name = "clk-mt6797-img",
> > +   .of_match_table = of_match_clk_mt6797_img,
> > +   },
> > +};
> > +
> > +builtin_platform_driver(clk_mt6797_img_drv);
> > diff --git a/drivers/clk/mediatek/clk-mt6797-mm.c 
> > b/drivers/clk/mediatek/clk-mt6797-mm.c
> > new file mode 100644
> > index 000..77f0342
> > --- /dev/null
> > +++ 

Re: [PATCH 4/4] clk: mediatek: Add MT6797 clock support

[Mars Cheng]

Hi Stephen

Thanks for your review. Response inlined.

On Thu, 2016-09-08 at 12:50 -0700, Stephen Boyd wrote:
> On 09/08/2016 03:49 AM, Mars Cheng wrote:
> > Add MT6797 clock support, include topckgen, apmixedsys,
> > infracfg and subsystem clocks.
> >
> > Signed-off-by: Mars Cheng 
> > ---
> >  arch/arm64/boot/dts/mediatek/mt6797.dtsi |   66 ++-
> 
> Please don't combine dts and clk driver changes together. We generally
> don't take dts changes through clk tree.

OK, will separate clk driver in single submit next time.

> 
> > diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
> > index 5aa6204..ce91ecb 100644
> > --- a/drivers/clk/mediatek/Kconfig
> > +++ b/drivers/clk/mediatek/Kconfig
> > @@ -56,6 +56,42 @@ config COMMON_CLK_MT2701_BDPSYS
> > ---help---
> >   This driver supports Mediatek MT2701 bdpsys clocks.
> >  
> 
> What tree is this based on?
Also 4.8-rc1, will base on clk-next to sent the patch.

> 
> > +config COMMON_CLK_MT6797
> > +   bool "Clock driver for Mediatek MT6797"
> > +   depends on COMMON_CLK
> 
> This sort of depends shouldn't be necessary.
> 

Got it. Will fix like this:
+config COMMON_CLK_MT6797
+   bool "Clock driver for Mediatek MT6797"
+   select COMMON_CLK_MEDIATEK
+   default ARCH_MEDIATEK
+   ---help---
+ This driver supports Mediatek MT6797 basic clocks.

> > +   select COMMON_CLK_MEDIATEK
> > +   default ARCH_MEDIATEK
> > +   ---help---
> > + This driver supports Mediatek MT6797 basic clocks.
> > +
> >
> >
> > diff --git a/drivers/clk/mediatek/clk-mt6797-img.c 
> > b/drivers/clk/mediatek/clk-mt6797-img.c
> > new file mode 100644
> > index 000..4ecd201
> > --- /dev/null
> > +++ b/drivers/clk/mediatek/clk-mt6797-img.c
> > @@ -0,0 +1,87 @@
> > +/* Copyright (c) 2016 MediaTek Inc.
> > + * Author: Kevin Chen 
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License version 2 as
> > + * published by the Free Software Foundation.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#include 
> 
> clk-provider.h?

Sure. Will fix it.

> 
> > +#include 
> > +#include 
> > +
> > +#include "clk-mtk.h"
> > +#include "clk-gate.h"
> > +
> > +static const struct mtk_gate_regs img_cg_regs = {
> > +   .set_ofs = 0x0004,
> > +   .clr_ofs = 0x0008,
> > +   .sta_ofs = 0x,
> > +};
> > +
> > +#define GATE_IMG(_id, _name, _parent, _shift) {\
> > +   .id = _id,  \
> > +   .name = _name,  \
> > +   .parent_name = _parent, \
> > +   .regs = _cg_regs,   \
> > +   .shift = _shift,\
> > +   .ops = _clk_gate_ops_setclr,\
> > +   }
> > +
> > +static const struct mtk_gate img_clks[] = {
> > +   GATE_IMG(CLK_IMG_FDVT, "img_fdvt", "mm_sel", 11),
> > +   GATE_IMG(CLK_IMG_DPE, "img_dpe", "mm_sel", 10),
> > +   GATE_IMG(CLK_IMG_DIP, "img_dip", "mm_sel", 6),
> > +   GATE_IMG(CLK_IMG_LARB6, "img_larb6", "mm_sel", 0),
> > +};
> > +
> > +static int mtk_imgsys_init(struct device *dev)
> > +{
> > +   struct clk_onecell_data *clk_data;
> > +   int r;
> > +
> > +   clk_data = mtk_alloc_clk_data(CLK_IMG_NR);
> > +   if (!clk_data) {
> > +   pr_err("%s: alloc failed\n", __func__);
> 
> Allocations already print a big error message so this is useless.

OK, will just return error code.

> 
> > +   goto alloc_err;
> > +   }
> > +
> > +   mtk_clk_register_gates(dev->of_node, img_clks, ARRAY_SIZE(img_clks),
> > +  clk_data);
> > +
> > +   r = of_clk_add_provider(dev->of_node, of_clk_src_onecell_get,
> > +   clk_data);
> > +   if (r)
> > +   pr_err("%s: could not register clock provider: %d\n",
> > +  __func__, r);
> > +
> > +   return r;
> > +
> > +alloc_err:
> > +   return -ENOMEM;
> > +}
> > +
> > +static const struct of_device_id of_match_clk_mt6797_img[] = {
> > +   { .compatible = "mediatek,mt6797-imgsys", },
> > +   {}
> > +};
> > +
> > +static int clk_mt6797_img_probe(struct platform_device *pdev)
> > +{
> > +   return mtk_imgsys_init(>dev);
> > +}
> > +
> > +static struct platform_driver clk_mt6797_img_drv = {
> > +   .probe = clk_mt6797_img_probe,
> > +   .driver = {
> > +   .name = "clk-mt6797-img",
> > +   .of_match_table = of_match_clk_mt6797_img,
> > +   },
> > +};
> > +
> > +builtin_platform_driver(clk_mt6797_img_drv);
> > diff --git a/drivers/clk/mediatek/clk-mt6797-mm.c 
> > b/drivers/clk/mediatek/clk-mt6797-mm.c
> > new file mode 100644
> > index 000..77f0342
> > --- /dev/null
> > +++ b/drivers/clk/mediatek/clk-mt6797-mm.c
> > @@ -0,0 

Re: [PATCH 4/4] clk: mediatek: Add MT6797 clock support

[Stephen Boyd]

On 09/08/2016 03:49 AM, Mars Cheng wrote:
> Add MT6797 clock support, include topckgen, apmixedsys,
> infracfg and subsystem clocks.
>
> Signed-off-by: Mars Cheng 
> ---
>  arch/arm64/boot/dts/mediatek/mt6797.dtsi |   66 ++-

Please don't combine dts and clk driver changes together. We generally
don't take dts changes through clk tree.

> diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
> index 5aa6204..ce91ecb 100644
> --- a/drivers/clk/mediatek/Kconfig
> +++ b/drivers/clk/mediatek/Kconfig
> @@ -56,6 +56,42 @@ config COMMON_CLK_MT2701_BDPSYS
>   ---help---
> This driver supports Mediatek MT2701 bdpsys clocks.
>  

What tree is this based on?

> +config COMMON_CLK_MT6797
> + bool "Clock driver for Mediatek MT6797"
> + depends on COMMON_CLK

This sort of depends shouldn't be necessary.

> + select COMMON_CLK_MEDIATEK
> + default ARCH_MEDIATEK
> + ---help---
> +   This driver supports Mediatek MT6797 basic clocks.
> +
>
>
> diff --git a/drivers/clk/mediatek/clk-mt6797-img.c 
> b/drivers/clk/mediatek/clk-mt6797-img.c
> new file mode 100644
> index 000..4ecd201
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt6797-img.c
> @@ -0,0 +1,87 @@
> +/* Copyright (c) 2016 MediaTek Inc.
> + * Author: Kevin Chen 
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#include 

clk-provider.h?

> +#include 
> +#include 
> +
> +#include "clk-mtk.h"
> +#include "clk-gate.h"
> +
> +static const struct mtk_gate_regs img_cg_regs = {
> + .set_ofs = 0x0004,
> + .clr_ofs = 0x0008,
> + .sta_ofs = 0x,
> +};
> +
> +#define GATE_IMG(_id, _name, _parent, _shift) {  \
> + .id = _id,  \
> + .name = _name,  \
> + .parent_name = _parent, \
> + .regs = _cg_regs,   \
> + .shift = _shift,\
> + .ops = _clk_gate_ops_setclr,\
> + }
> +
> +static const struct mtk_gate img_clks[] = {
> + GATE_IMG(CLK_IMG_FDVT, "img_fdvt", "mm_sel", 11),
> + GATE_IMG(CLK_IMG_DPE, "img_dpe", "mm_sel", 10),
> + GATE_IMG(CLK_IMG_DIP, "img_dip", "mm_sel", 6),
> + GATE_IMG(CLK_IMG_LARB6, "img_larb6", "mm_sel", 0),
> +};
> +
> +static int mtk_imgsys_init(struct device *dev)
> +{
> + struct clk_onecell_data *clk_data;
> + int r;
> +
> + clk_data = mtk_alloc_clk_data(CLK_IMG_NR);
> + if (!clk_data) {
> + pr_err("%s: alloc failed\n", __func__);

Allocations already print a big error message so this is useless.

> + goto alloc_err;
> + }
> +
> + mtk_clk_register_gates(dev->of_node, img_clks, ARRAY_SIZE(img_clks),
> +clk_data);
> +
> + r = of_clk_add_provider(dev->of_node, of_clk_src_onecell_get,
> + clk_data);
> + if (r)
> + pr_err("%s: could not register clock provider: %d\n",
> +__func__, r);
> +
> + return r;
> +
> +alloc_err:
> + return -ENOMEM;
> +}
> +
> +static const struct of_device_id of_match_clk_mt6797_img[] = {
> + { .compatible = "mediatek,mt6797-imgsys", },
> + {}
> +};
> +
> +static int clk_mt6797_img_probe(struct platform_device *pdev)
> +{
> + return mtk_imgsys_init(>dev);
> +}
> +
> +static struct platform_driver clk_mt6797_img_drv = {
> + .probe = clk_mt6797_img_probe,
> + .driver = {
> + .name = "clk-mt6797-img",
> + .of_match_table = of_match_clk_mt6797_img,
> + },
> +};
> +
> +builtin_platform_driver(clk_mt6797_img_drv);
> diff --git a/drivers/clk/mediatek/clk-mt6797-mm.c 
> b/drivers/clk/mediatek/clk-mt6797-mm.c
> new file mode 100644
> index 000..77f0342
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt6797-mm.c
> @@ -0,0 +1,146 @@
> +/*
> + * Copyright (c) 2016 MediaTek Inc.
> + * Author: Kevin Chen 
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#include 

clk-provider.h?

> +#include 
> +#include 
> +
> +#include "clk-mtk.h"
> 

Re: [PATCH 4/4] clk: mediatek: Add MT6797 clock support

[Stephen Boyd]

On 09/08/2016 03:49 AM, Mars Cheng wrote:
> Add MT6797 clock support, include topckgen, apmixedsys,
> infracfg and subsystem clocks.
>
> Signed-off-by: Mars Cheng 
> ---
>  arch/arm64/boot/dts/mediatek/mt6797.dtsi |   66 ++-

Please don't combine dts and clk driver changes together. We generally
don't take dts changes through clk tree.

> diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
> index 5aa6204..ce91ecb 100644
> --- a/drivers/clk/mediatek/Kconfig
> +++ b/drivers/clk/mediatek/Kconfig
> @@ -56,6 +56,42 @@ config COMMON_CLK_MT2701_BDPSYS
>   ---help---
> This driver supports Mediatek MT2701 bdpsys clocks.
>  

What tree is this based on?

> +config COMMON_CLK_MT6797
> + bool "Clock driver for Mediatek MT6797"
> + depends on COMMON_CLK

This sort of depends shouldn't be necessary.

> + select COMMON_CLK_MEDIATEK
> + default ARCH_MEDIATEK
> + ---help---
> +   This driver supports Mediatek MT6797 basic clocks.
> +
>
>
> diff --git a/drivers/clk/mediatek/clk-mt6797-img.c 
> b/drivers/clk/mediatek/clk-mt6797-img.c
> new file mode 100644
> index 000..4ecd201
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt6797-img.c
> @@ -0,0 +1,87 @@
> +/* Copyright (c) 2016 MediaTek Inc.
> + * Author: Kevin Chen 
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#include 

clk-provider.h?

> +#include 
> +#include 
> +
> +#include "clk-mtk.h"
> +#include "clk-gate.h"
> +
> +static const struct mtk_gate_regs img_cg_regs = {
> + .set_ofs = 0x0004,
> + .clr_ofs = 0x0008,
> + .sta_ofs = 0x,
> +};
> +
> +#define GATE_IMG(_id, _name, _parent, _shift) {  \
> + .id = _id,  \
> + .name = _name,  \
> + .parent_name = _parent, \
> + .regs = _cg_regs,   \
> + .shift = _shift,\
> + .ops = _clk_gate_ops_setclr,\
> + }
> +
> +static const struct mtk_gate img_clks[] = {
> + GATE_IMG(CLK_IMG_FDVT, "img_fdvt", "mm_sel", 11),
> + GATE_IMG(CLK_IMG_DPE, "img_dpe", "mm_sel", 10),
> + GATE_IMG(CLK_IMG_DIP, "img_dip", "mm_sel", 6),
> + GATE_IMG(CLK_IMG_LARB6, "img_larb6", "mm_sel", 0),
> +};
> +
> +static int mtk_imgsys_init(struct device *dev)
> +{
> + struct clk_onecell_data *clk_data;
> + int r;
> +
> + clk_data = mtk_alloc_clk_data(CLK_IMG_NR);
> + if (!clk_data) {
> + pr_err("%s: alloc failed\n", __func__);

Allocations already print a big error message so this is useless.

> + goto alloc_err;
> + }
> +
> + mtk_clk_register_gates(dev->of_node, img_clks, ARRAY_SIZE(img_clks),
> +clk_data);
> +
> + r = of_clk_add_provider(dev->of_node, of_clk_src_onecell_get,
> + clk_data);
> + if (r)
> + pr_err("%s: could not register clock provider: %d\n",
> +__func__, r);
> +
> + return r;
> +
> +alloc_err:
> + return -ENOMEM;
> +}
> +
> +static const struct of_device_id of_match_clk_mt6797_img[] = {
> + { .compatible = "mediatek,mt6797-imgsys", },
> + {}
> +};
> +
> +static int clk_mt6797_img_probe(struct platform_device *pdev)
> +{
> + return mtk_imgsys_init(>dev);
> +}
> +
> +static struct platform_driver clk_mt6797_img_drv = {
> + .probe = clk_mt6797_img_probe,
> + .driver = {
> + .name = "clk-mt6797-img",
> + .of_match_table = of_match_clk_mt6797_img,
> + },
> +};
> +
> +builtin_platform_driver(clk_mt6797_img_drv);
> diff --git a/drivers/clk/mediatek/clk-mt6797-mm.c 
> b/drivers/clk/mediatek/clk-mt6797-mm.c
> new file mode 100644
> index 000..77f0342
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt6797-mm.c
> @@ -0,0 +1,146 @@
> +/*
> + * Copyright (c) 2016 MediaTek Inc.
> + * Author: Kevin Chen 
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#include 

clk-provider.h?

> +#include 
> +#include 
> +
> +#include "clk-mtk.h"
> +#include "clk-gate.h"
> +
> +static const struct mtk_gate_regs mm0_cg_regs = {

[PATCH 4/4] clk: mediatek: Add MT6797 clock support

[Mars Cheng]

Add MT6797 clock support, include topckgen, apmixedsys,
infracfg and subsystem clocks.

Signed-off-by: Mars Cheng 
---
 arch/arm64/boot/dts/mediatek/mt6797.dtsi |   66 ++-
 drivers/clk/mediatek/Kconfig |   36 ++
 drivers/clk/mediatek/Makefile|5 +
 drivers/clk/mediatek/clk-mt6797-img.c|   87 
 drivers/clk/mediatek/clk-mt6797-mm.c |  146 ++
 drivers/clk/mediatek/clk-mt6797-vdec.c   |  102 +
 drivers/clk/mediatek/clk-mt6797-venc.c   |   86 
 drivers/clk/mediatek/clk-mt6797.c|  716 ++
 include/dt-bindings/clock/mt6797-clk.h   |  281 
 9 files changed, 1514 insertions(+), 11 deletions(-)
 create mode 100644 drivers/clk/mediatek/clk-mt6797-img.c
 create mode 100644 drivers/clk/mediatek/clk-mt6797-mm.c
 create mode 100644 drivers/clk/mediatek/clk-mt6797-vdec.c
 create mode 100644 drivers/clk/mediatek/clk-mt6797-venc.c
 create mode 100644 drivers/clk/mediatek/clk-mt6797.c
 create mode 100644 include/dt-bindings/clock/mt6797-clk.h

diff --git a/arch/arm64/boot/dts/mediatek/mt6797.dtsi 
b/arch/arm64/boot/dts/mediatek/mt6797.dtsi
index 66f6442..75d3877 100644
--- a/arch/arm64/boot/dts/mediatek/mt6797.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt6797.dtsi
@@ -10,6 +10,7 @@
  * GNU General Public License for more details.
  */
 
+#include 
 #include 
 #include 
 
@@ -113,12 +114,6 @@
clock-output-names = "clk32k";
};
 
-   uart_clk: dummy26m {
-   compatible = "fixed-clock";
-   clock-frequency = <2600>;
-   #clock-cells = <0>;
-   };
-
timer {
compatible = "arm,armv8-timer";
interrupt-parent = <>;
@@ -132,6 +127,24 @@
 (GIC_CPU_MASK_SIMPLE(10) | IRQ_TYPE_LEVEL_LOW)>;
};
 
+   topckgen: topckgen@1000 {
+   compatible = "mediatek,mt6797-topckgen";
+   reg = <0 0x1000 0 0x1000>;
+   #clock-cells = <1>;
+   };
+
+   infrasys: infracfg_ao@10001000 {
+   compatible = "mediatek,mt6797-infracfg", "syscon";
+   reg = <0 0x10001000 0 0x1000>;
+   #clock-cells = <1>;
+   };
+
+   apmixedsys: apmixed@1000c000 {
+   compatible = "mediatek,mt6797-apmixedsys";
+   reg = <0 0x1000c000 0 0x1000>;
+   #clock-cells = <1>;
+   };
+
sysirq: intpol-controller@10200620 {
compatible = "mediatek,mt6797-sysirq",
 "mediatek,mt6577-sysirq";
@@ -148,7 +161,9 @@
 "mediatek,mt6577-uart";
reg = <0 0x11002000 0 0x400>;
interrupts = ;
-   clocks = <_clk>;
+   clocks = < CLK_INFRA_UART0>,
+< CLK_INFRA_AP_DMA>;
+   clock-names = "baud", "bus";
status = "disabled";
};
 
@@ -157,7 +172,9 @@
 "mediatek,mt6577-uart";
reg = <0 0x11003000 0 0x400>;
interrupts = ;
-   clocks = <_clk>;
+   clocks = < CLK_INFRA_UART1>,
+< CLK_INFRA_AP_DMA>;
+   clock-names = "baud", "bus";
status = "disabled";
};
 
@@ -166,7 +183,9 @@
 "mediatek,mt6577-uart";
reg = <0 0x11004000 0 0x400>;
interrupts = ;
-   clocks = <_clk>;
+   clocks = < CLK_INFRA_UART2>,
+< CLK_INFRA_AP_DMA>;
+   clock-names = "baud", "bus";
status = "disabled";
};
 
@@ -175,10 +194,36 @@
 "mediatek,mt6577-uart";
reg = <0 0x11005000 0 0x400>;
interrupts = ;
-   clocks = <_clk>;
+   clocks = < CLK_INFRA_UART3>,
+< CLK_INFRA_AP_DMA>;
+   clock-names = "baud", "bus";
status = "disabled";
};
 
+   mmsys: mmsys_config@1400 {
+   compatible = "mediatek,mt6797-mmsys", "syscon";
+   reg = <0 0x1400 0 0x1000>;
+   #clock-cells = <1>;
+   };
+
+   imgsys: imgsys_config@1500  {
+   compatible = "mediatek,mt6797-imgsys", "syscon";
+   reg = <0 0x1500 0 0x1000>;
+   #clock-cells = <1>;
+   };
+
+   vdecsys: vdec_gcon@1600 {
+   compatible = "mediatek,mt6797-vdecsys", "syscon";
+   reg = <0 0x1600 0 0x1>;
+   #clock-cells = <1>;
+   };
+
+   vencsys: venc_gcon@1700 {
+   compatible = "mediatek,mt6797-vencsys", "syscon";
+   reg = <0 0x1700 0 0x1000>;
+   #clock-cells = <1>;
+   };
+
gic: interrupt-controller@1900 {
compatible = "arm,gic-v3";

[PATCH 4/4] clk: mediatek: Add MT6797 clock support

[Mars Cheng]

Add MT6797 clock support, include topckgen, apmixedsys,
infracfg and subsystem clocks.

Signed-off-by: Mars Cheng 
---
 arch/arm64/boot/dts/mediatek/mt6797.dtsi |   66 ++-
 drivers/clk/mediatek/Kconfig |   36 ++
 drivers/clk/mediatek/Makefile|5 +
 drivers/clk/mediatek/clk-mt6797-img.c|   87 
 drivers/clk/mediatek/clk-mt6797-mm.c |  146 ++
 drivers/clk/mediatek/clk-mt6797-vdec.c   |  102 +
 drivers/clk/mediatek/clk-mt6797-venc.c   |   86 
 drivers/clk/mediatek/clk-mt6797.c|  716 ++
 include/dt-bindings/clock/mt6797-clk.h   |  281 
 9 files changed, 1514 insertions(+), 11 deletions(-)
 create mode 100644 drivers/clk/mediatek/clk-mt6797-img.c
 create mode 100644 drivers/clk/mediatek/clk-mt6797-mm.c
 create mode 100644 drivers/clk/mediatek/clk-mt6797-vdec.c
 create mode 100644 drivers/clk/mediatek/clk-mt6797-venc.c
 create mode 100644 drivers/clk/mediatek/clk-mt6797.c
 create mode 100644 include/dt-bindings/clock/mt6797-clk.h

diff --git a/arch/arm64/boot/dts/mediatek/mt6797.dtsi 
b/arch/arm64/boot/dts/mediatek/mt6797.dtsi
index 66f6442..75d3877 100644
--- a/arch/arm64/boot/dts/mediatek/mt6797.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt6797.dtsi
@@ -10,6 +10,7 @@
  * GNU General Public License for more details.
  */
 
+#include 
 #include 
 #include 
 
@@ -113,12 +114,6 @@
clock-output-names = "clk32k";
};
 
-   uart_clk: dummy26m {
-   compatible = "fixed-clock";
-   clock-frequency = <2600>;
-   #clock-cells = <0>;
-   };
-
timer {
compatible = "arm,armv8-timer";
interrupt-parent = <>;
@@ -132,6 +127,24 @@
 (GIC_CPU_MASK_SIMPLE(10) | IRQ_TYPE_LEVEL_LOW)>;
};
 
+   topckgen: topckgen@1000 {
+   compatible = "mediatek,mt6797-topckgen";
+   reg = <0 0x1000 0 0x1000>;
+   #clock-cells = <1>;
+   };
+
+   infrasys: infracfg_ao@10001000 {
+   compatible = "mediatek,mt6797-infracfg", "syscon";
+   reg = <0 0x10001000 0 0x1000>;
+   #clock-cells = <1>;
+   };
+
+   apmixedsys: apmixed@1000c000 {
+   compatible = "mediatek,mt6797-apmixedsys";
+   reg = <0 0x1000c000 0 0x1000>;
+   #clock-cells = <1>;
+   };
+
sysirq: intpol-controller@10200620 {
compatible = "mediatek,mt6797-sysirq",
 "mediatek,mt6577-sysirq";
@@ -148,7 +161,9 @@
 "mediatek,mt6577-uart";
reg = <0 0x11002000 0 0x400>;
interrupts = ;
-   clocks = <_clk>;
+   clocks = < CLK_INFRA_UART0>,
+< CLK_INFRA_AP_DMA>;
+   clock-names = "baud", "bus";
status = "disabled";
};
 
@@ -157,7 +172,9 @@
 "mediatek,mt6577-uart";
reg = <0 0x11003000 0 0x400>;
interrupts = ;
-   clocks = <_clk>;
+   clocks = < CLK_INFRA_UART1>,
+< CLK_INFRA_AP_DMA>;
+   clock-names = "baud", "bus";
status = "disabled";
};
 
@@ -166,7 +183,9 @@
 "mediatek,mt6577-uart";
reg = <0 0x11004000 0 0x400>;
interrupts = ;
-   clocks = <_clk>;
+   clocks = < CLK_INFRA_UART2>,
+< CLK_INFRA_AP_DMA>;
+   clock-names = "baud", "bus";
status = "disabled";
};
 
@@ -175,10 +194,36 @@
 "mediatek,mt6577-uart";
reg = <0 0x11005000 0 0x400>;
interrupts = ;
-   clocks = <_clk>;
+   clocks = < CLK_INFRA_UART3>,
+< CLK_INFRA_AP_DMA>;
+   clock-names = "baud", "bus";
status = "disabled";
};
 
+   mmsys: mmsys_config@1400 {
+   compatible = "mediatek,mt6797-mmsys", "syscon";
+   reg = <0 0x1400 0 0x1000>;
+   #clock-cells = <1>;
+   };
+
+   imgsys: imgsys_config@1500  {
+   compatible = "mediatek,mt6797-imgsys", "syscon";
+   reg = <0 0x1500 0 0x1000>;
+   #clock-cells = <1>;
+   };
+
+   vdecsys: vdec_gcon@1600 {
+   compatible = "mediatek,mt6797-vdecsys", "syscon";
+   reg = <0 0x1600 0 0x1>;
+   #clock-cells = <1>;
+   };
+
+   vencsys: venc_gcon@1700 {
+   compatible = "mediatek,mt6797-vencsys", "syscon";
+   reg = <0 0x1700 0 0x1000>;
+   #clock-cells = <1>;
+   };
+
gic: interrupt-controller@1900 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
@@ -189,5