[PATCH 4.4 101/107] clk: tegra: Fix PLL_U post divider and initial rate on Tegra30

4.4-stable review patch. If anyone has any objections, please let me know. -- From: Lucas Stach commit 797097301860c64b63346d068ba4fe4992bd5021 upstream. The post divider value in the frequency table is wrong as it would lead to the PLL producing an output rate of 960 MHz

[PATCH 4.4 101/107] clk: tegra: Fix PLL_U post divider and initial rate on Tegra30

4.4-stable review patch. If anyone has any objections, please let me know. -- From: Lucas Stach commit 797097301860c64b63346d068ba4fe4992bd5021 upstream. The post divider value in the frequency table is wrong as it would lead to the PLL producing an output rate of 960 MHz