Re: [PATCH 5/5] 2.6.13-rc5-mm1, driver for IBM Automatic Server Restart watchdog
On 229, 08 17, 2005 at 01:14:15PM -0700, Andrew Morton wrote:
> Andrey Panin <[EMAIL PROTECTED]> wrote:
> >
> >
> > This patch adds driver for IBM Automatic Server Restart watchdog hardware
> > found in some IBM eServer xSeries machines. This driver is based on the ugly
> > driver provided by IBM. Driver was tested on IBM eServer 226.
> >
> > ...
> > +
> > + case ASMTYPE_JASPER:
> > + type = "Jaspers ";
> > +
> > + /* FIXME: need to use pci_config_lock here, but it's not
> > exported */
>
> That's gregkh material.
>
> > +
> > +/* spin_lock_irqsave(_config_lock, flags);*/
> > +
> > + /* Select the SuperIO chip in the PCI I/O port register */
> > + outl(0x8000f858, 0xcf8);
> > +
> > + /*
> > +* Read the base address for the SuperIO chip.
> > +* Only the lower 16 bits are valid, but the address is word
> > +* aligned so the last bit must be masked off.
> > +*/
> > + asr_base = inl(0xcfc) & 0xfffe;
> > +
> > +/* spin_unlock_irqrestore(_config_lock, flags);*/
> >
> > ...
> >
> > +static int asr_ioctl(struct inode *inode, struct file *file,
> > +unsigned int cmd, unsigned long arg)
> > +{
> > + static const struct watchdog_info ident = {
> > + .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT |
> > + WDIOF_MAGICCLOSE,
> > + .identity = "IBM ASR"
> > + };
> > + void __user *argp = (void __user *)arg;
> > + int __user *p = argp;
> > + int heartbeat;
> > +
> > + switch (cmd) {
> > + case WDIOC_GETSUPPORT:
> > + return copy_to_user(argp, , sizeof(ident)) ?
> > + -EFAULT : 0;
> > +
> > + case WDIOC_GETSTATUS:
> > + case WDIOC_GETBOOTSTATUS:
> > + return put_user(0, p);
> > +
> > + case WDIOC_KEEPALIVE:
> > + asr_toggle();
> > + return 0;
> > +
> > +
> > + case WDIOC_SETTIMEOUT:
> > + if (get_user(heartbeat, p))
> > + return -EFAULT;
> > + /* Fall */
> > +
> > + case WDIOC_GETTIMEOUT:
> > + heartbeat = 256;
> > + return put_user(heartbeat, p);
>
> Something very wrong is happening with WDIOC_SETTIMEOUT and
> WDIOC_GETTIMEOUT. They're both no-ops and the effect of WDIOC_SETTIMEOUT
> is immidiately overwritten.
Hardware has fixed timeout value, so WDIOC_SETTIMEOUT is noop and
WDIOC_GETTIMEOUT
always returns 256.
--
Andrey Panin| Linux and UNIX system administrator
[EMAIL PROTECTED] | PGP key: wwwkeys.pgp.net
signature.asc
Description: Digital signature
Re: [PATCH 5/5] 2.6.13-rc5-mm1, driver for IBM Automatic Server Restart watchdog
Andrey Panin <[EMAIL PROTECTED]> wrote:
>
>
> This patch adds driver for IBM Automatic Server Restart watchdog hardware
> found in some IBM eServer xSeries machines. This driver is based on the ugly
> driver provided by IBM. Driver was tested on IBM eServer 226.
>
> ...
> +
> + case ASMTYPE_JASPER:
> + type = "Jaspers ";
> +
> + /* FIXME: need to use pci_config_lock here, but it's not
> exported */
That's gregkh material.
> +
> +/* spin_lock_irqsave(_config_lock, flags);*/
> +
> + /* Select the SuperIO chip in the PCI I/O port register */
> + outl(0x8000f858, 0xcf8);
> +
> + /*
> + * Read the base address for the SuperIO chip.
> + * Only the lower 16 bits are valid, but the address is word
> + * aligned so the last bit must be masked off.
> + */
> + asr_base = inl(0xcfc) & 0xfffe;
> +
> +/* spin_unlock_irqrestore(_config_lock, flags);*/
>
> ...
>
> +static int asr_ioctl(struct inode *inode, struct file *file,
> + unsigned int cmd, unsigned long arg)
> +{
> + static const struct watchdog_info ident = {
> + .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT |
> + WDIOF_MAGICCLOSE,
> + .identity = "IBM ASR"
> + };
> + void __user *argp = (void __user *)arg;
> + int __user *p = argp;
> + int heartbeat;
> +
> + switch (cmd) {
> + case WDIOC_GETSUPPORT:
> + return copy_to_user(argp, , sizeof(ident)) ?
> + -EFAULT : 0;
> +
> + case WDIOC_GETSTATUS:
> + case WDIOC_GETBOOTSTATUS:
> + return put_user(0, p);
> +
> + case WDIOC_KEEPALIVE:
> + asr_toggle();
> + return 0;
> +
> +
> + case WDIOC_SETTIMEOUT:
> + if (get_user(heartbeat, p))
> + return -EFAULT;
> + /* Fall */
> +
> + case WDIOC_GETTIMEOUT:
> + heartbeat = 256;
> + return put_user(heartbeat, p);
Something very wrong is happening with WDIOC_SETTIMEOUT and
WDIOC_GETTIMEOUT. They're both no-ops and the effect of WDIOC_SETTIMEOUT
is immidiately overwritten.
-
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the body of a message to [EMAIL PROTECTED]
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 5/5] 2.6.13-rc5-mm1, driver for IBM Automatic Server Restart watchdog
Andrey Panin [EMAIL PROTECTED] wrote:
This patch adds driver for IBM Automatic Server Restart watchdog hardware
found in some IBM eServer xSeries machines. This driver is based on the ugly
driver provided by IBM. Driver was tested on IBM eServer 226.
...
+
+ case ASMTYPE_JASPER:
+ type = Jaspers ;
+
+ /* FIXME: need to use pci_config_lock here, but it's not
exported */
That's gregkh material.
+
+/* spin_lock_irqsave(pci_config_lock, flags);*/
+
+ /* Select the SuperIO chip in the PCI I/O port register */
+ outl(0x8000f858, 0xcf8);
+
+ /*
+ * Read the base address for the SuperIO chip.
+ * Only the lower 16 bits are valid, but the address is word
+ * aligned so the last bit must be masked off.
+ */
+ asr_base = inl(0xcfc) 0xfffe;
+
+/* spin_unlock_irqrestore(pci_config_lock, flags);*/
...
+static int asr_ioctl(struct inode *inode, struct file *file,
+ unsigned int cmd, unsigned long arg)
+{
+ static const struct watchdog_info ident = {
+ .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT |
+ WDIOF_MAGICCLOSE,
+ .identity = IBM ASR
+ };
+ void __user *argp = (void __user *)arg;
+ int __user *p = argp;
+ int heartbeat;
+
+ switch (cmd) {
+ case WDIOC_GETSUPPORT:
+ return copy_to_user(argp, ident, sizeof(ident)) ?
+ -EFAULT : 0;
+
+ case WDIOC_GETSTATUS:
+ case WDIOC_GETBOOTSTATUS:
+ return put_user(0, p);
+
+ case WDIOC_KEEPALIVE:
+ asr_toggle();
+ return 0;
+
+
+ case WDIOC_SETTIMEOUT:
+ if (get_user(heartbeat, p))
+ return -EFAULT;
+ /* Fall */
+
+ case WDIOC_GETTIMEOUT:
+ heartbeat = 256;
+ return put_user(heartbeat, p);
Something very wrong is happening with WDIOC_SETTIMEOUT and
WDIOC_GETTIMEOUT. They're both no-ops and the effect of WDIOC_SETTIMEOUT
is immidiately overwritten.
-
To unsubscribe from this list: send the line unsubscribe linux-kernel in
the body of a message to [EMAIL PROTECTED]
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 5/5] 2.6.13-rc5-mm1, driver for IBM Automatic Server Restart watchdog
On 229, 08 17, 2005 at 01:14:15PM -0700, Andrew Morton wrote:
Andrey Panin [EMAIL PROTECTED] wrote:
This patch adds driver for IBM Automatic Server Restart watchdog hardware
found in some IBM eServer xSeries machines. This driver is based on the ugly
driver provided by IBM. Driver was tested on IBM eServer 226.
...
+
+ case ASMTYPE_JASPER:
+ type = Jaspers ;
+
+ /* FIXME: need to use pci_config_lock here, but it's not
exported */
That's gregkh material.
+
+/* spin_lock_irqsave(pci_config_lock, flags);*/
+
+ /* Select the SuperIO chip in the PCI I/O port register */
+ outl(0x8000f858, 0xcf8);
+
+ /*
+* Read the base address for the SuperIO chip.
+* Only the lower 16 bits are valid, but the address is word
+* aligned so the last bit must be masked off.
+*/
+ asr_base = inl(0xcfc) 0xfffe;
+
+/* spin_unlock_irqrestore(pci_config_lock, flags);*/
...
+static int asr_ioctl(struct inode *inode, struct file *file,
+unsigned int cmd, unsigned long arg)
+{
+ static const struct watchdog_info ident = {
+ .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT |
+ WDIOF_MAGICCLOSE,
+ .identity = IBM ASR
+ };
+ void __user *argp = (void __user *)arg;
+ int __user *p = argp;
+ int heartbeat;
+
+ switch (cmd) {
+ case WDIOC_GETSUPPORT:
+ return copy_to_user(argp, ident, sizeof(ident)) ?
+ -EFAULT : 0;
+
+ case WDIOC_GETSTATUS:
+ case WDIOC_GETBOOTSTATUS:
+ return put_user(0, p);
+
+ case WDIOC_KEEPALIVE:
+ asr_toggle();
+ return 0;
+
+
+ case WDIOC_SETTIMEOUT:
+ if (get_user(heartbeat, p))
+ return -EFAULT;
+ /* Fall */
+
+ case WDIOC_GETTIMEOUT:
+ heartbeat = 256;
+ return put_user(heartbeat, p);
Something very wrong is happening with WDIOC_SETTIMEOUT and
WDIOC_GETTIMEOUT. They're both no-ops and the effect of WDIOC_SETTIMEOUT
is immidiately overwritten.
Hardware has fixed timeout value, so WDIOC_SETTIMEOUT is noop and
WDIOC_GETTIMEOUT
always returns 256.
--
Andrey Panin| Linux and UNIX system administrator
[EMAIL PROTECTED] | PGP key: wwwkeys.pgp.net
signature.asc
Description: Digital signature
[PATCH 5/5] 2.6.13-rc5-mm1, driver for IBM Automatic Server Restart watchdog
This patch adds driver for IBM Automatic Server Restart watchdog hardware
found in some IBM eServer xSeries machines. This driver is based on the ugly
driver provided by IBM. Driver was tested on IBM eServer 226.
Signed-off-by: Andrey Panin <[EMAIL PROTECTED]>
drivers/char/watchdog/Kconfig | 10 +
drivers/char/watchdog/Makefile |1
drivers/char/watchdog/ibmasr.c | 407 +
3 files changed, 418 insertions(+)
diff -urdpN linux-2.6.13-rc5-mm1.vanilla/drivers/char/watchdog/ibmasr.c
linux-2.6.13-rc5-mm1/drivers/char/watchdog/ibmasr.c
--- linux-2.6.13-rc5-mm1.vanilla/drivers/char/watchdog/ibmasr.c 1970-01-01
03:00:00.0 +0300
+++ linux-2.6.13-rc5-mm1/drivers/char/watchdog/ibmasr.c 2005-08-10
11:43:45.0 +0400
@@ -0,0 +1,407 @@
+/*
+ * IBM Automatic Server Restart driver.
+ *
+ * Copyright (c) 2005 Andrey Panin <[EMAIL PROTECTED]>
+ *
+ * Based on driver written by Pete Reynolds.
+ * Copyright (c) IBM Corporation, 1998-2004.
+ *
+ * This software may be used and distributed according to the terms
+ * of the GNU Public License, incorporated herein by reference.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+
+
+enum {
+ ASMTYPE_UNKNOWN,
+ ASMTYPE_TOPAZ,
+ ASMTYPE_JASPER,
+ ASMTYPE_PEARL,
+ ASMTYPE_JUNIPER,
+ ASMTYPE_SPRUCE,
+};
+
+#define PFX "ibmasr: "
+
+#define TOPAZ_ASR_REG_OFFSET 4
+#define TOPAZ_ASR_TOGGLE 0x40
+#define TOPAZ_ASR_DISABLE 0x80
+
+/* PEARL ASR S/W REGISTER SUPERIO PORT ADDRESSES */
+#define PEARL_BASE 0xe04
+#define PEARL_WRITE0xe06
+#define PEARL_READ 0xe07
+
+#define PEARL_ASR_DISABLE_MASK 0x80/* bit 7: disable = 1, enable = 0 */
+#define PEARL_ASR_TOGGLE_MASK 0x40/* bit 6: 0, then 1, then 0 */
+
+/* JASPER OFFSET FROM SIO BASE ADDR TO ASR S/W REGISTERS. */
+#define JASPER_ASR_REG_OFFSET 0x38
+
+#define JASPER_ASR_DISABLE_MASK0x01/* bit 0: disable = 1, enable =
0 */
+#define JASPER_ASR_TOGGLE_MASK 0x02/* bit 1: 0, then 1, then 0 */
+
+#define JUNIPER_BASE_ADDRESS 0x54b /* Base address of Juniper ASR */
+#define JUNIPER_ASR_DISABLE_MASK 0x01 /* bit 0: disable = 1 enable = 0 */
+#define JUNIPER_ASR_TOGGLE_MASK0x02/* bit 1: 0, then 1, then 0 */
+
+#define SPRUCE_BASE_ADDRESS0x118e /* Base address of Spruce ASR */
+#define SPRUCE_ASR_DISABLE_MASK0x01/* bit 1: disable = 1 enable =
0 */
+#define SPRUCE_ASR_TOGGLE_MASK 0x02/* bit 0: 0, then 1, then 0 */
+
+
+static int nowayout = WATCHDOG_NOWAYOUT;
+
+static unsigned long asr_is_open;
+static char asr_expect_close;
+
+static unsigned int asr_type, asr_base, asr_length;
+static unsigned int asr_read_addr, asr_write_addr;
+static unsigned char asr_toggle_mask, asr_disable_mask;
+
+static void asr_toggle(void)
+{
+ unsigned char reg = inb(asr_read_addr);
+
+ outb(reg & ~asr_toggle_mask, asr_write_addr);
+ reg = inb(asr_read_addr);
+
+ outb(reg | asr_toggle_mask, asr_write_addr);
+ reg = inb(asr_read_addr);
+
+ outb(reg & ~asr_toggle_mask, asr_write_addr);
+ reg = inb(asr_read_addr);
+}
+
+static void asr_enable(void)
+{
+ unsigned char reg;
+
+ if (asr_type == ASMTYPE_TOPAZ) {
+ /* asr_write_addr == asr_read_addr */
+ reg = inb(asr_read_addr);
+ outb(reg & ~(TOPAZ_ASR_TOGGLE | TOPAZ_ASR_DISABLE),
+asr_read_addr);
+ } else {
+ /*
+* First make sure the hardware timer is reset by toggling
+* ASR hardware timer line.
+*/
+ asr_toggle();
+
+ reg = inb(asr_read_addr);
+ outb(reg & ~asr_disable_mask, asr_write_addr);
+ }
+ reg = inb(asr_read_addr);
+}
+
+static void asr_disable(void)
+{
+ unsigned char reg = inb(asr_read_addr);
+
+ if (asr_type == ASMTYPE_TOPAZ)
+ /* asr_write_addr == asr_read_addr */
+ outb(reg | TOPAZ_ASR_TOGGLE | TOPAZ_ASR_DISABLE,
+asr_read_addr);
+ else {
+ outb(reg | asr_toggle_mask, asr_write_addr);
+ reg = inb(asr_read_addr);
+
+ outb(reg | asr_disable_mask, asr_write_addr);
+ }
+ reg = inb(asr_read_addr);
+}
+
+static int __init asr_get_base_address(void)
+{
+ unsigned char low, high;
+ const char *type = "";
+
+ asr_length = 1;
+
+ switch (asr_type) {
+ case ASMTYPE_TOPAZ:
+ /* SELECT SuperIO CHIP FOR QUERYING (WRITE 0x07 TO BOTH 0x2E
and 0x2F) */
+ outb(0x07, 0x2e);
+ outb(0x07, 0x2f);
+
+ /* SELECT AND READ THE HIGH-NIBBLE OF THE GPIO BASE ADDRESS */
+ outb(0x60, 0x2e);
+ high = inb(0x2f);
+
+ /* SELECT AND READ THE LOW-NIBBLE OF THE GPIO BASE ADDRESS */
+
[PATCH 5/5] 2.6.13-rc5-mm1, driver for IBM Automatic Server Restart watchdog
This patch adds driver for IBM Automatic Server Restart watchdog hardware
found in some IBM eServer xSeries machines. This driver is based on the ugly
driver provided by IBM. Driver was tested on IBM eServer 226.
Signed-off-by: Andrey Panin [EMAIL PROTECTED]
drivers/char/watchdog/Kconfig | 10 +
drivers/char/watchdog/Makefile |1
drivers/char/watchdog/ibmasr.c | 407 +
3 files changed, 418 insertions(+)
diff -urdpN linux-2.6.13-rc5-mm1.vanilla/drivers/char/watchdog/ibmasr.c
linux-2.6.13-rc5-mm1/drivers/char/watchdog/ibmasr.c
--- linux-2.6.13-rc5-mm1.vanilla/drivers/char/watchdog/ibmasr.c 1970-01-01
03:00:00.0 +0300
+++ linux-2.6.13-rc5-mm1/drivers/char/watchdog/ibmasr.c 2005-08-10
11:43:45.0 +0400
@@ -0,0 +1,407 @@
+/*
+ * IBM Automatic Server Restart driver.
+ *
+ * Copyright (c) 2005 Andrey Panin [EMAIL PROTECTED]
+ *
+ * Based on driver written by Pete Reynolds.
+ * Copyright (c) IBM Corporation, 1998-2004.
+ *
+ * This software may be used and distributed according to the terms
+ * of the GNU Public License, incorporated herein by reference.
+ */
+
+#include linux/config.h
+#include linux/fs.h
+#include linux/kernel.h
+#include linux/slab.h
+#include linux/module.h
+#include linux/pci.h
+#include linux/timer.h
+#include linux/miscdevice.h
+#include linux/watchdog.h
+#include linux/dmi.h
+
+#include asm/io.h
+#include asm/uaccess.h
+
+
+enum {
+ ASMTYPE_UNKNOWN,
+ ASMTYPE_TOPAZ,
+ ASMTYPE_JASPER,
+ ASMTYPE_PEARL,
+ ASMTYPE_JUNIPER,
+ ASMTYPE_SPRUCE,
+};
+
+#define PFX ibmasr:
+
+#define TOPAZ_ASR_REG_OFFSET 4
+#define TOPAZ_ASR_TOGGLE 0x40
+#define TOPAZ_ASR_DISABLE 0x80
+
+/* PEARL ASR S/W REGISTER SUPERIO PORT ADDRESSES */
+#define PEARL_BASE 0xe04
+#define PEARL_WRITE0xe06
+#define PEARL_READ 0xe07
+
+#define PEARL_ASR_DISABLE_MASK 0x80/* bit 7: disable = 1, enable = 0 */
+#define PEARL_ASR_TOGGLE_MASK 0x40/* bit 6: 0, then 1, then 0 */
+
+/* JASPER OFFSET FROM SIO BASE ADDR TO ASR S/W REGISTERS. */
+#define JASPER_ASR_REG_OFFSET 0x38
+
+#define JASPER_ASR_DISABLE_MASK0x01/* bit 0: disable = 1, enable =
0 */
+#define JASPER_ASR_TOGGLE_MASK 0x02/* bit 1: 0, then 1, then 0 */
+
+#define JUNIPER_BASE_ADDRESS 0x54b /* Base address of Juniper ASR */
+#define JUNIPER_ASR_DISABLE_MASK 0x01 /* bit 0: disable = 1 enable = 0 */
+#define JUNIPER_ASR_TOGGLE_MASK0x02/* bit 1: 0, then 1, then 0 */
+
+#define SPRUCE_BASE_ADDRESS0x118e /* Base address of Spruce ASR */
+#define SPRUCE_ASR_DISABLE_MASK0x01/* bit 1: disable = 1 enable =
0 */
+#define SPRUCE_ASR_TOGGLE_MASK 0x02/* bit 0: 0, then 1, then 0 */
+
+
+static int nowayout = WATCHDOG_NOWAYOUT;
+
+static unsigned long asr_is_open;
+static char asr_expect_close;
+
+static unsigned int asr_type, asr_base, asr_length;
+static unsigned int asr_read_addr, asr_write_addr;
+static unsigned char asr_toggle_mask, asr_disable_mask;
+
+static void asr_toggle(void)
+{
+ unsigned char reg = inb(asr_read_addr);
+
+ outb(reg ~asr_toggle_mask, asr_write_addr);
+ reg = inb(asr_read_addr);
+
+ outb(reg | asr_toggle_mask, asr_write_addr);
+ reg = inb(asr_read_addr);
+
+ outb(reg ~asr_toggle_mask, asr_write_addr);
+ reg = inb(asr_read_addr);
+}
+
+static void asr_enable(void)
+{
+ unsigned char reg;
+
+ if (asr_type == ASMTYPE_TOPAZ) {
+ /* asr_write_addr == asr_read_addr */
+ reg = inb(asr_read_addr);
+ outb(reg ~(TOPAZ_ASR_TOGGLE | TOPAZ_ASR_DISABLE),
+asr_read_addr);
+ } else {
+ /*
+* First make sure the hardware timer is reset by toggling
+* ASR hardware timer line.
+*/
+ asr_toggle();
+
+ reg = inb(asr_read_addr);
+ outb(reg ~asr_disable_mask, asr_write_addr);
+ }
+ reg = inb(asr_read_addr);
+}
+
+static void asr_disable(void)
+{
+ unsigned char reg = inb(asr_read_addr);
+
+ if (asr_type == ASMTYPE_TOPAZ)
+ /* asr_write_addr == asr_read_addr */
+ outb(reg | TOPAZ_ASR_TOGGLE | TOPAZ_ASR_DISABLE,
+asr_read_addr);
+ else {
+ outb(reg | asr_toggle_mask, asr_write_addr);
+ reg = inb(asr_read_addr);
+
+ outb(reg | asr_disable_mask, asr_write_addr);
+ }
+ reg = inb(asr_read_addr);
+}
+
+static int __init asr_get_base_address(void)
+{
+ unsigned char low, high;
+ const char *type = ;
+
+ asr_length = 1;
+
+ switch (asr_type) {
+ case ASMTYPE_TOPAZ:
+ /* SELECT SuperIO CHIP FOR QUERYING (WRITE 0x07 TO BOTH 0x2E
and 0x2F) */
+ outb(0x07, 0x2e);
+ outb(0x07, 0x2f);
+
+ /* SELECT AND READ THE HIGH-NIBBLE OF THE GPIO BASE ADDRESS */
+
