On 03/21/2013 10:31 PM, Arnd Bergmann wrote:
On Thursday 21 March 2013, Thomas Petazzoni wrote:
In the mean time can we do something like:
soc {
compatible = "simple-bus";
range =<...>;
[... all the peripherals ...]
};
with
On 03/21/2013 10:41 PM, Jason Gunthorpe wrote:
On Thu, Mar 21, 2013 at 10:15:23PM +0100, Thomas Petazzoni wrote:
Dear Jason Gunthorpe,
On Thu, 21 Mar 2013 14:55:45 -0600, Jason Gunthorpe wrote:
Or, better, locate all the internal registers above 8G and use
contiguous DRAM mapping from 0 ->
On Thu, Mar 21, 2013 at 10:15:23PM +0100, Thomas Petazzoni wrote:
> Dear Jason Gunthorpe,
>
> On Thu, 21 Mar 2013 14:55:45 -0600, Jason Gunthorpe wrote:
>
> > Or, better, locate all the internal registers above 8G and use
> > contiguous DRAM mapping from 0 -> 8GB
>
> I see two potential issues
On Thursday 21 March 2013, Thomas Petazzoni wrote:
> In the mean time can we do something like:
>
> soc {
> compatible = "simple-bus";
> range = <...>;
>
> [... all the peripherals ...]
> };
>
> with the range = <...> property
Dear Andrew Lunn,
On Thu, 21 Mar 2013 21:37:51 +0100, Andrew Lunn wrote:
> > And I'm not sure the SDRAM address decoding windows allows to split the
> > first 4 GB of RAM into two areas, one that would be mapped starting at
> > physical address 0x0, and another area that would be mapped at a
> >
Dear Jason Gunthorpe,
On Thu, 21 Mar 2013 14:55:45 -0600, Jason Gunthorpe wrote:
> Or, better, locate all the internal registers above 8G and use
> contiguous DRAM mapping from 0 -> 8GB
I see two potential issues with this idea:
*) It only works when LPAE is enabled, so we would have to have
Dear Andrew Lunn,
On Thu, 21 Mar 2013 21:37:51 +0100, Andrew Lunn wrote:
> > And I'm not sure the SDRAM address decoding windows allows to split the
> > first 4 GB of RAM into two areas, one that would be mapped starting at
> > physical address 0x0, and another area that would be mapped at a
> >
On Thu, Mar 21, 2013 at 09:22:36PM +0100, Thomas Petazzoni wrote:
> And I'm not sure the SDRAM address decoding windows allows to split the
> first 4 GB of RAM into two areas, one that would be mapped starting at
> physical address 0x0, and another area that would be mapped at a
> different
On Thu, Mar 21, 2013 at 09:22:36PM +0100, Thomas Petazzoni wrote:
> Dear Andrew Lunn,
>
> On Thu, 21 Mar 2013 21:15:33 +0100, Andrew Lunn wrote:
>
> > Could you recommend a document which introduces LPAE.
> >
> > Only being able to address 7GB seems a bit odd to me. I kind of
> > expected you
On Thu, Mar 21, 2013 at 09:22:36PM +0100, Thomas Petazzoni wrote:
> Dear Andrew Lunn,
>
> On Thu, 21 Mar 2013 21:15:33 +0100, Andrew Lunn wrote:
>
> > Could you recommend a document which introduces LPAE.
> >
> > Only being able to address 7GB seems a bit odd to me. I kind of
> > expected you
Dear Andrew Lunn,
On Thu, 21 Mar 2013 21:15:33 +0100, Andrew Lunn wrote:
> Could you recommend a document which introduces LPAE.
>
> Only being able to address 7GB seems a bit odd to me. I kind of
> expected you set up the translation tables to map a page in the 32 bit
> address range to any
> /*
> - * 4 GB of plug-in RAM modules by default but only 3GB
> - * are visible, the amount of memory available can be
> - * changed by the bootloader according the size of the
> - * module actually plugged
> + * 8 GB
Dear Arnd Bergmann,
On Thu, 21 Mar 2013 19:03:52 +, Arnd Bergmann wrote:
> On Thursday 21 March 2013, Rob Herring wrote:
> > > soc {
> > > - #address-cells = <1>;
> > > - #size-cells = <1>;
> > > + #address-cells = <2>;
> > > + #size-cells
On Thursday 21 March 2013, Rob Herring wrote:
> > soc {
> > - #address-cells = <1>;
> > - #size-cells = <1>;
> > + #address-cells = <2>;
> > + #size-cells = <2>;
>
> If all the addresses for the soc bus are below 4GB or even within a 4GB
>
On 03/21/2013 11:26 AM, Gregory CLEMENT wrote:
> In order to be able to use more than 4GB of RAM when the LPAE is
> activated, the dts must be converted in 64 bits.
>
> Armada XP and Armada 370 share a dtsi file which have also be
> converted to 64 bits. This lead to convert all the device tree
In order to be able to use more than 4GB of RAM when the LPAE is
activated, the dts must be converted in 64 bits.
Armada XP and Armada 370 share a dtsi file which have also be
converted to 64 bits. This lead to convert all the device tree files
to 64 bits even the one used for Armada 370 (which
In order to be able to use more than 4GB of RAM when the LPAE is
activated, the dts must be converted in 64 bits.
Armada XP and Armada 370 share a dtsi file which have also be
converted to 64 bits. This lead to convert all the device tree files
to 64 bits even the one used for Armada 370 (which
On 03/21/2013 11:26 AM, Gregory CLEMENT wrote:
In order to be able to use more than 4GB of RAM when the LPAE is
activated, the dts must be converted in 64 bits.
Armada XP and Armada 370 share a dtsi file which have also be
converted to 64 bits. This lead to convert all the device tree files
On Thursday 21 March 2013, Rob Herring wrote:
soc {
- #address-cells = 1;
- #size-cells = 1;
+ #address-cells = 2;
+ #size-cells = 2;
If all the addresses for the soc bus are below 4GB or even within a 4GB
range if using the
Dear Arnd Bergmann,
On Thu, 21 Mar 2013 19:03:52 +, Arnd Bergmann wrote:
On Thursday 21 March 2013, Rob Herring wrote:
soc {
- #address-cells = 1;
- #size-cells = 1;
+ #address-cells = 2;
+ #size-cells = 2;
If all the
/*
- * 4 GB of plug-in RAM modules by default but only 3GB
- * are visible, the amount of memory available can be
- * changed by the bootloader according the size of the
- * module actually plugged
+ * 8 GB of
Dear Andrew Lunn,
On Thu, 21 Mar 2013 21:15:33 +0100, Andrew Lunn wrote:
Could you recommend a document which introduces LPAE.
Only being able to address 7GB seems a bit odd to me. I kind of
expected you set up the translation tables to map a page in the 32 bit
address range to any
On Thu, Mar 21, 2013 at 09:22:36PM +0100, Thomas Petazzoni wrote:
Dear Andrew Lunn,
On Thu, 21 Mar 2013 21:15:33 +0100, Andrew Lunn wrote:
Could you recommend a document which introduces LPAE.
Only being able to address 7GB seems a bit odd to me. I kind of
expected you set up the
On Thu, Mar 21, 2013 at 09:22:36PM +0100, Thomas Petazzoni wrote:
Dear Andrew Lunn,
On Thu, 21 Mar 2013 21:15:33 +0100, Andrew Lunn wrote:
Could you recommend a document which introduces LPAE.
Only being able to address 7GB seems a bit odd to me. I kind of
expected you set up the
On Thu, Mar 21, 2013 at 09:22:36PM +0100, Thomas Petazzoni wrote:
And I'm not sure the SDRAM address decoding windows allows to split the
first 4 GB of RAM into two areas, one that would be mapped starting at
physical address 0x0, and another area that would be mapped at a
different address
Dear Andrew Lunn,
On Thu, 21 Mar 2013 21:37:51 +0100, Andrew Lunn wrote:
And I'm not sure the SDRAM address decoding windows allows to split the
first 4 GB of RAM into two areas, one that would be mapped starting at
physical address 0x0, and another area that would be mapped at a
Dear Jason Gunthorpe,
On Thu, 21 Mar 2013 14:55:45 -0600, Jason Gunthorpe wrote:
Or, better, locate all the internal registers above 8G and use
contiguous DRAM mapping from 0 - 8GB
I see two potential issues with this idea:
*) It only works when LPAE is enabled, so we would have to have
Dear Andrew Lunn,
On Thu, 21 Mar 2013 21:37:51 +0100, Andrew Lunn wrote:
And I'm not sure the SDRAM address decoding windows allows to split the
first 4 GB of RAM into two areas, one that would be mapped starting at
physical address 0x0, and another area that would be mapped at a
On Thursday 21 March 2013, Thomas Petazzoni wrote:
In the mean time can we do something like:
soc {
compatible = simple-bus;
range = ...;
[... all the peripherals ...]
};
with the range = ... property converting the
On Thu, Mar 21, 2013 at 10:15:23PM +0100, Thomas Petazzoni wrote:
Dear Jason Gunthorpe,
On Thu, 21 Mar 2013 14:55:45 -0600, Jason Gunthorpe wrote:
Or, better, locate all the internal registers above 8G and use
contiguous DRAM mapping from 0 - 8GB
I see two potential issues with this
On 03/21/2013 10:41 PM, Jason Gunthorpe wrote:
On Thu, Mar 21, 2013 at 10:15:23PM +0100, Thomas Petazzoni wrote:
Dear Jason Gunthorpe,
On Thu, 21 Mar 2013 14:55:45 -0600, Jason Gunthorpe wrote:
Or, better, locate all the internal registers above 8G and use
contiguous DRAM mapping from 0 -
On 03/21/2013 10:31 PM, Arnd Bergmann wrote:
On Thursday 21 March 2013, Thomas Petazzoni wrote:
In the mean time can we do something like:
soc {
compatible = simple-bus;
range =...;
[... all the peripherals ...]
};
with the
32 matches
Mail list logo
