On Tue, Oct 20, 2015 at 04:00:21PM +0200, Thomas Petazzoni wrote:
> Hello,
>
> On Tue, 20 Oct 2015 15:23:55 +0200, Thomas Petazzoni wrote:
>
> > +/*
> > + * Overall diagram of the Armada XP interrupt controller:
> > + *
> > + *To CPU 0 To CPU 1
> > + *
> > + * /\
Hello,
On Tue, 20 Oct 2015 15:23:55 +0200, Thomas Petazzoni wrote:
> +/*
> + * Overall diagram of the Armada XP interrupt controller:
> + *
> + *To CPU 0 To CPU 1
> + *
> + * /\ /\
> + * || ||
> + * +---+
Hi Thomas,
On mar., oct. 20 2015, Thomas Petazzoni
wrote:
> Since the overall logic of the driver to handle the global and per-CPU
> masking of the interrupts is far from trivial, this commit adds a long
> comment detailing how the hardware operates and what strategy the
> driver implements
Since the overall logic of the driver to handle the global and per-CPU
masking of the interrupts is far from trivial, this commit adds a long
comment detailing how the hardware operates and what strategy the
driver implements on top of that.
Signed-off-by: Thomas Petazzoni
---
Hi Thomas,
On mar., oct. 20 2015, Thomas Petazzoni
wrote:
> Since the overall logic of the driver to handle the global and per-CPU
> masking of the interrupts is far from trivial, this commit adds a long
> comment detailing how the hardware operates and
Hello,
On Tue, 20 Oct 2015 15:23:55 +0200, Thomas Petazzoni wrote:
> +/*
> + * Overall diagram of the Armada XP interrupt controller:
> + *
> + *To CPU 0 To CPU 1
> + *
> + * /\ /\
> + * || ||
> + * +---+
On Tue, Oct 20, 2015 at 04:00:21PM +0200, Thomas Petazzoni wrote:
> Hello,
>
> On Tue, 20 Oct 2015 15:23:55 +0200, Thomas Petazzoni wrote:
>
> > +/*
> > + * Overall diagram of the Armada XP interrupt controller:
> > + *
> > + *To CPU 0 To CPU 1
> > + *
> > + * /\
Since the overall logic of the driver to handle the global and per-CPU
masking of the interrupts is far from trivial, this commit adds a long
comment detailing how the hardware operates and what strategy the
driver implements on top of that.
Signed-off-by: Thomas Petazzoni
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