[PATCH 5/5] perf, x86: Move NMI clearing to end of PMI handler after the counter registers are reset

2013-02-18 Thread Andi Kleen
From: Andi Kleen This avoids some problems with spurious PMIs on Haswell. Haswell seems to behave more like P4 in this regard. Do the same thing as the P4 perf handler by unmasking the NMI only at the end. Shouldn't make any difference for earlier family 6 cores. Tested on Haswell, IvyBridge,

[PATCH 5/5] perf, x86: Move NMI clearing to end of PMI handler after the counter registers are reset

2013-02-18 Thread Andi Kleen
From: Andi Kleen a...@linux.intel.com This avoids some problems with spurious PMIs on Haswell. Haswell seems to behave more like P4 in this regard. Do the same thing as the P4 perf handler by unmasking the NMI only at the end. Shouldn't make any difference for earlier family 6 cores. Tested on

[PATCH 5/5] perf, x86: Move NMI clearing to end of PMI handler after the counter registers are reset

2013-02-13 Thread Andi Kleen
From: Andi Kleen This avoids some problems with spurious PMIs on Haswell. Haswell seems to behave more like P4 in this regard. Do the same thing as the P4 perf handler by unmasking the NMI only at the end. Shouldn't make any difference for earlier family 6 cores. Tested on Haswell, IvyBridge,

Re: [PATCH 5/5] perf, x86: Move NMI clearing to end of PMI handler after the counter registers are reset

2013-02-13 Thread Ingo Molnar
* Andi Kleen wrote: > On Tue, Feb 12, 2013 at 09:43:46AM +0100, Ingo Molnar wrote: > > Was this stress-tested on all affected main CPU types, or only > > on Haswell? > > I tested it on Haswell and Ivy Bridge. I can also try Westmere > and a Saltwell(Atom), but for the majority of other

Re: [PATCH 5/5] perf, x86: Move NMI clearing to end of PMI handler after the counter registers are reset

2013-02-13 Thread Ingo Molnar
* Andi Kleen a...@firstfloor.org wrote: On Tue, Feb 12, 2013 at 09:43:46AM +0100, Ingo Molnar wrote: Was this stress-tested on all affected main CPU types, or only on Haswell? I tested it on Haswell and Ivy Bridge. I can also try Westmere and a Saltwell(Atom), but for the majority of

[PATCH 5/5] perf, x86: Move NMI clearing to end of PMI handler after the counter registers are reset

2013-02-13 Thread Andi Kleen
From: Andi Kleen a...@linux.intel.com This avoids some problems with spurious PMIs on Haswell. Haswell seems to behave more like P4 in this regard. Do the same thing as the P4 perf handler by unmasking the NMI only at the end. Shouldn't make any difference for earlier family 6 cores. Tested on

[PATCH 5/5] perf, x86: Move NMI clearing to end of PMI handler after the counter registers are reset

2013-02-12 Thread Andi Kleen
From: Andi Kleen This avoids some problems with spurious PMIs on Haswell. Haswell seems to behave more like P4 in this regard. Do the same thing as the P4 perf handler by unmasking the NMI only at the end. Shouldn't make any difference for earlier family 6 cores. Tested on Haswell, IvyBridge,

Re: [PATCH 5/5] perf, x86: Move NMI clearing to end of PMI handler after the counter registers are reset

2013-02-12 Thread Andi Kleen
On Tue, Feb 12, 2013 at 09:43:46AM +0100, Ingo Molnar wrote: > Was this stress-tested on all affected main CPU types, or only > on Haswell? I tested it on Haswell and Ivy Bridge. I can also try Westmere and a Saltwell(Atom), but for the majority of other family 6 systems I'll need to rely on the

Re: [PATCH 5/5] perf, x86: Move NMI clearing to end of PMI handler after the counter registers are reset

2013-02-12 Thread Ingo Molnar
* Andi Kleen wrote: > From: Andi Kleen > > This avoids some problems with spurious PMIs on Haswell. > Haswell seems to behave more like P4 in this regard. Do > the same thing as the P4 perf handler by unmasking > the NMI only at the end. Shouldn't make any difference > for earlier non P4

Re: [PATCH 5/5] perf, x86: Move NMI clearing to end of PMI handler after the counter registers are reset

2013-02-12 Thread Ingo Molnar
* Andi Kleen a...@firstfloor.org wrote: From: Andi Kleen a...@linux.intel.com This avoids some problems with spurious PMIs on Haswell. Haswell seems to behave more like P4 in this regard. Do the same thing as the P4 perf handler by unmasking the NMI only at the end. Shouldn't make any

Re: [PATCH 5/5] perf, x86: Move NMI clearing to end of PMI handler after the counter registers are reset

2013-02-12 Thread Andi Kleen
On Tue, Feb 12, 2013 at 09:43:46AM +0100, Ingo Molnar wrote: Was this stress-tested on all affected main CPU types, or only on Haswell? I tested it on Haswell and Ivy Bridge. I can also try Westmere and a Saltwell(Atom), but for the majority of other family 6 systems I'll need to rely on the

[PATCH 5/5] perf, x86: Move NMI clearing to end of PMI handler after the counter registers are reset

2013-02-12 Thread Andi Kleen
From: Andi Kleen a...@linux.intel.com This avoids some problems with spurious PMIs on Haswell. Haswell seems to behave more like P4 in this regard. Do the same thing as the P4 perf handler by unmasking the NMI only at the end. Shouldn't make any difference for earlier family 6 cores. Tested on

[PATCH 5/5] perf, x86: Move NMI clearing to end of PMI handler after the counter registers are reset

2013-02-07 Thread Andi Kleen
From: Andi Kleen This avoids some problems with spurious PMIs on Haswell. Haswell seems to behave more like P4 in this regard. Do the same thing as the P4 perf handler by unmasking the NMI only at the end. Shouldn't make any difference for earlier non P4 cores. Signed-off-by: Andi Kleen ---

[PATCH 5/5] perf, x86: Move NMI clearing to end of PMI handler after the counter registers are reset

2013-02-07 Thread Andi Kleen
From: Andi Kleen a...@linux.intel.com This avoids some problems with spurious PMIs on Haswell. Haswell seems to behave more like P4 in this regard. Do the same thing as the P4 perf handler by unmasking the NMI only at the end. Shouldn't make any difference for earlier non P4 cores.

[PATCH 5/5] perf, x86: Move NMI clearing to end of PMI handler after the counter registers are reset

2013-02-04 Thread Andi Kleen
From: Andi Kleen This avoids some problems with spurious PMIs on Haswell. Haswell seems to behave more like P4 in this regard. Do the same thing as the P4 perf handler by unmasking the NMI only at the end. Shouldn't make any difference for earlier non P4 cores. Signed-off-by: Andi Kleen ---

[PATCH 5/5] perf, x86: Move NMI clearing to end of PMI handler after the counter registers are reset

2013-02-04 Thread Andi Kleen
From: Andi Kleen a...@linux.intel.com This avoids some problems with spurious PMIs on Haswell. Haswell seems to behave more like P4 in this regard. Do the same thing as the P4 perf handler by unmasking the NMI only at the end. Shouldn't make any difference for earlier non P4 cores.

[PATCH 5/5] perf, x86: Move NMI clearing to end of PMI handler after the counter registers are reset

2013-02-01 Thread Andi Kleen
From: Andi Kleen This avoids some problems with spurious PMIs on Haswell. Haswell seems to behave more like P4 in this regard. Do the same thing as the P4 perf handler by unmasking the NMI only at the end. Shouldn't make any difference for earlier non P4 cores. Signed-off-by: Andi Kleen ---

[PATCH 5/5] perf, x86: Move NMI clearing to end of PMI handler after the counter registers are reset

2013-02-01 Thread Andi Kleen
From: Andi Kleen a...@linux.intel.com This avoids some problems with spurious PMIs on Haswell. Haswell seems to behave more like P4 in this regard. Do the same thing as the P4 perf handler by unmasking the NMI only at the end. Shouldn't make any difference for earlier non P4 cores.