On 2018-12-13 8:17 a.m., Bjorn Helgaas wrote:
>> static void init_pff(struct switchtec_dev *stdev)
>> @@ -1294,6 +1367,19 @@ static int switchtec_init_pci(struct switchtec_dev
>> *stdev,
>>
>> pci_set_drvdata(pdev, stdev);
>>
>> +if (!use_dma_mrpc)
>> +return 0;
>> +
On Mon, Dec 10, 2018 at 05:12:24PM +0800, Wesley Sheng wrote:
> MRPC normal mode requires the host to read the MRPC command status and
> output data from BAR. This results in high latency responses from the
> Memory Read TLP and potential Completion Timeout (CTO).
>
> MRPC DMA mode implementation
On Wed, Dec 12, 2018 at 03:58:22PM -0700, Logan Gunthorpe wrote:
> On 2018-12-12 3:52 p.m., Bjorn Helgaas wrote:
> > On Mon, Dec 10, 2018 at 05:12:24PM +0800, Wesley Sheng wrote:
> >> MRPC normal mode requires the host to read the MRPC command status and
> >> output data from BAR. This results in
On 2018-12-12 3:52 p.m., Bjorn Helgaas wrote:
> On Mon, Dec 10, 2018 at 05:12:24PM +0800, Wesley Sheng wrote:
>> MRPC normal mode requires the host to read the MRPC command status and
>> output data from BAR. This results in high latency responses from the
>> Memory Read TLP and potential
On Mon, Dec 10, 2018 at 05:12:24PM +0800, Wesley Sheng wrote:
> MRPC normal mode requires the host to read the MRPC command status and
> output data from BAR. This results in high latency responses from the
> Memory Read TLP and potential Completion Timeout (CTO).
>
> MRPC DMA mode implementation
MRPC normal mode requires the host to read the MRPC command status and
output data from BAR. This results in high latency responses from the
Memory Read TLP and potential Completion Timeout (CTO).
MRPC DMA mode implementation includes:
Macro definitions for registers and data structures
MRPC normal mode requires the host to read the MRPC command status and
output data from BAR. This results in high latency responses from the
Memory Read TLP and potential Completion Timeout (CTO).
MRPC DMA mode implementation includes:
Macro definitions for registers and data structures
MRPC normal mode requires the host to read the MRPC command status and
output data from BAR. This results in high latency responses from the
Memory Read TLP and potential Completion Timeout (CTO).
MRPC DMA mode implementation includes:
Macro definitions for registers and data structures
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