From: John Garry <john.ga...@huawei.com>
[ Upstream commit 2bf797be81fa808f05f1a7a65916619132256a27 ]
The "briefdescription" for event 0x35 has a typo - fix it.
Fixes: d35c595bf005 ("perf vendor events arm64: Revise core JSON events for
eMAG")
Signed-off-by: John Garry <john.ga...@huawei.com>
Acked-by: Will Deacon <w...@kernel.org>
Cc: James Clark <james.cl...@arm.com>
Cc: Jiri Olsa <jo...@redhat.com>
Cc: Leo Yan <leo....@linaro.org>
Cc: Mark Rutland <mark.rutl...@arm.com>
Cc: Mathieu Poirier <mathieu.poir...@linaro.org>
Cc: Nakamura, Shunsuke/中村 俊介 <nakamura.s...@fujitsu.com>
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux...@openeuler.org
Link:
https://lore.kernel.org/r/1611835236-34696-2-git-send-email-john.ga...@huawei.com
Signed-off-by: Arnaldo Carvalho de Melo <a...@redhat.com>
Signed-off-by: Sasha Levin <sas...@kernel.org>
---
tools/perf/pmu-events/arch/arm64/ampere/emag/cache.json | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tools/perf/pmu-events/arch/arm64/ampere/emag/cache.json
b/tools/perf/pmu-events/arch/arm64/ampere/emag/cache.json
index df9201434cb6a..b0a10a219b50d 100644
--- a/tools/perf/pmu-events/arch/arm64/ampere/emag/cache.json
+++ b/tools/perf/pmu-events/arch/arm64/ampere/emag/cache.json
@@ -114,7 +114,7 @@
"PublicDescription": "Level 2 access to instruciton TLB that caused a
page table walk. This event counts on any instruciton access which causes
L2I_TLB_REFILL to count",
"EventCode": "0x35",
"EventName": "L2I_TLB_ACCESS",
- "BriefDescription": "L2D TLB access"
+ "BriefDescription": "L2I TLB access"
},
{
"PublicDescription": "Branch target buffer misprediction",
--
2.27.0
