Re: [PATCH AUTOSEL 5.2 17/42] MIPS: lantiq: update the clock alias' for the mainline PCIe PHY driver

2019-10-05 Thread Sasha Levin
On Sun, Sep 29, 2019 at 07:39:49PM +0200, Hauke Mehrtens wrote: On 9/29/19 7:32 PM, Sasha Levin wrote: From: Martin Blumenstingl [ Upstream commit ed90302be64a53d9031c8ce05428c358b16a5d96 ] The mainline PCIe PHY driver has it's own devicetree node. Update the clock alias so the mainline

Re: [PATCH AUTOSEL 5.2 17/42] MIPS: lantiq: update the clock alias' for the mainline PCIe PHY driver

2019-09-29 Thread Hauke Mehrtens
On 9/29/19 7:32 PM, Sasha Levin wrote: > From: Martin Blumenstingl > > [ Upstream commit ed90302be64a53d9031c8ce05428c358b16a5d96 ] > > The mainline PCIe PHY driver has it's own devicetree node. Update the > clock alias so the mainline driver finds the clocks. > > The first PCIe PHY is located

[PATCH AUTOSEL 5.2 17/42] MIPS: lantiq: update the clock alias' for the mainline PCIe PHY driver

2019-09-29 Thread Sasha Levin
From: Martin Blumenstingl [ Upstream commit ed90302be64a53d9031c8ce05428c358b16a5d96 ] The mainline PCIe PHY driver has it's own devicetree node. Update the clock alias so the mainline driver finds the clocks. The first PCIe PHY is located at 0x1f106800 and exists on VRX200, ARX300 and GRX390.