On Thu, Sep 19, 2019 at 01:37:08PM +0200, Greg KH wrote:
> Why is this being submitted for drivers/staging/ and not the "real" part
> of the kernel tree?
Hi Greg!
I sent v2 of the patchset, but it does not need to be part of the
staging tree. I CC-ed de...@driverdev.osuosl.org for reference.
On 19-09-19, 13:37, Greg KH wrote:
> On Thu, Sep 19, 2019 at 11:59:11AM +0200, Alexander Gordeev wrote:
> > The Avalon-MM DMA Interface for PCIe is a design found in hard IPs for
> > Intel Arria, Cyclone or Stratix FPGAs. It transfers data between on-chip
> > memory and system memory. This RFC is
On Thu, Sep 19, 2019 at 11:59:11AM +0200, Alexander Gordeev wrote:
> The Avalon-MM DMA Interface for PCIe is a design found in hard IPs for
> Intel Arria, Cyclone or Stratix FPGAs. It transfers data between on-chip
> memory and system memory. This RFC is an attempt to provide a generic API:
>
>
The Avalon-MM DMA Interface for PCIe is a design found in hard IPs for
Intel Arria, Cyclone or Stratix FPGAs. It transfers data between on-chip
memory and system memory. This RFC is an attempt to provide a generic API:
typedef void (*avalon_dma_xfer_callback)(void *dma_async_param);
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