Hi Sibi,
On 19. 5. 27. 오후 5:23, Sibi Sankar wrote:
> Hey Chanwoo,
>
> Thanks a lot for reviewing the patch. Like I
> had indicated earlier we decided to go with
> a simpler approach instead on qualcomm SoCs.
> I am happy to re-spin this patch with your
> comments addressed if we do find other
Hey Chanwoo,
Thanks a lot for reviewing the patch. Like I
had indicated earlier we decided to go with
a simpler approach instead on qualcomm SoCs.
I am happy to re-spin this patch with your
comments addressed if we do find other users
for this feature.
On 2019-04-12 13:09, Chanwoo Choi wrote:
Hi,
I agree this approach absolutely.
Just I add some comments. Please check it.
On 19. 3. 29. 오전 12:28, Sibi Sankar wrote:
> From: Saravana Kannan
>
> Many CPU architectures have caches that can scale independent of the
> CPUs. Frequency scaling of the caches is necessary to make sure the
From: Saravana Kannan
Many CPU architectures have caches that can scale independent of the
CPUs. Frequency scaling of the caches is necessary to make sure the cache
is not a performance bottleneck that leads to poor performance and
power. The same idea applies for RAM/DDR.
To achieve this, this
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