Re: [PATCH RFC v2 1/8] pinctrl: Add driver for Zynq

2014-11-02 Thread Sören Brinkmann 
On Thu, 2014-10-30 at 09:16AM +0100, Lothar Waßmann wrote:
> Hi,
> 
> Sören Brinkmann wrote:
> > On Wed, 2014-10-29 at 05:49AM +0100, Lothar Waßmann wrote:
> > > Hi,
> > > 
> > > Sören Brinkmann wrote:
> > > > On Tue, 2014-10-28 at 04:16PM +0100, Lothar Waßmann wrote:
> > > > > Hi,
> > > > > 
> > > > > Soren Brinkmann wrote:
> > > > > > Signed-off-by: Soren Brinkmann 
> > > > > > ---
> > > > > > changes since RFC:
> > > > > >  - use syscon/regmap to access registers in SLCR space
> > > > > >  - add pinctrl to zc702 DT
> > > > > >  - rebase to 3.18: rename enable -> set_mux
> > > > > >  - add kernel-doc
> > > > > >  - support pinconf
> > > > > >- supported attributes
> > > > > >  - pin-bias: pull up, tristate, disable
> > > > > >  - slew-rate: 0 == slow, 1 == fast; generic pinconf does not 
> > > > > > display
> > > > > >argument
> > > > > > 
> > > > > [...]
> > > > > > +struct zynq_pctrl_group zynq_pctrl_groups[] = {
> > > > > > +   DEFINE_ZYNQ_PINCTRL_GRP(ethernet0_0),
> > > > > > +   DEFINE_ZYNQ_PINCTRL_GRP(ethernet1_0),
> > > > > > +   DEFINE_ZYNQ_PINCTRL_GRP(mdio0_0),
> > > > > > +   DEFINE_ZYNQ_PINCTRL_GRP(mdio1_0),
> > > > > > +   DEFINE_ZYNQ_PINCTRL_GRP(qspi0_0),
> > > > > > +   DEFINE_ZYNQ_PINCTRL_GRP(qspi1_0),
> > > > > > +   DEFINE_ZYNQ_PINCTRL_GRP(qspi_fbclk),
> > > > > > +   DEFINE_ZYNQ_PINCTRL_GRP(qspi_cs1),
> > > > > > +   DEFINE_ZYNQ_PINCTRL_GRP(spi0_0),
> > > > > > +   DEFINE_ZYNQ_PINCTRL_GRP(spi0_1),
> > > > > > +   DEFINE_ZYNQ_PINCTRL_GRP(spi0_2),
> > > > > > +   DEFINE_ZYNQ_PINCTRL_GRP(spi1_0),
> > > > > > +   DEFINE_ZYNQ_PINCTRL_GRP(spi1_1),
> > > > > > +   DEFINE_ZYNQ_PINCTRL_GRP(spi1_2),
> > > > > > +   DEFINE_ZYNQ_PINCTRL_GRP(spi1_3),
> > > > > > +   DEFINE_ZYNQ_PINCTRL_GRP(sdio0_0),
> > > > > > +   DEFINE_ZYNQ_PINCTRL_GRP(sdio0_1),
> > > > > > +   DEFINE_ZYNQ_PINCTRL_GRP(sdio0_2),
> > > > > > +   DEFINE_ZYNQ_PINCTRL_GRP(sdio1_0),
> > > > > > +   DEFINE_ZYNQ_PINCTRL_GRP(sdio1_1),
> > > > > > +   DEFINE_ZYNQ_PINCTRL_GRP(sdio1_2),
> > > > > > +   DEFINE_ZYNQ_PINCTRL_GRP(sdio1_3),
> > > > > > +   DEFINE_ZYNQ_PINCTRL_GRP(sdio0_emio_wp),
> > > > > > +   DEFINE_ZYNQ_PINCTRL_GRP(sdio0_emio_cd),
> > > > > > +   DEFINE_ZYNQ_PINCTRL_GRP(sdio1_emio_wp),
> > > > > > +   DEFINE_ZYNQ_PINCTRL_GRP(sdio1_emio_cd),
> > > > > > +   DEFINE_ZYNQ_PINCTRL_GRP(smc0_nor),
> > > > > > +   DEFINE_ZYNQ_PINCTRL_GRP(smc0_nor_cs1),
> > > > > > +   DEFINE_ZYNQ_PINCTRL_GRP(smc0_nor_addr25),
> > > > > > +   DEFINE_ZYNQ_PINCTRL_GRP(smc0_nand),
> > > > > > +   DEFINE_ZYNQ_PINCTRL_GRP(can0_0),
> > > > > > +   DEFINE_ZYNQ_PINCTRL_GRP(can0_1),
> > > > > > +   DEFINE_ZYNQ_PINCTRL_GRP(can0_2),
> > > > > > +   DEFINE_ZYNQ_PINCTRL_GRP(can0_3),
> > > > > > +   DEFINE_ZYNQ_PINCTRL_GRP(can0_4),
> > > > > > +   DEFINE_ZYNQ_PINCTRL_GRP(can0_5),
> > > > > > +   DEFINE_ZYNQ_PINCTRL_GRP(can0_6),
> > > > > > +   DEFINE_ZYNQ_PINCTRL_GRP(can0_7),
> > > > > > +   DEFINE_ZYNQ_PINCTRL_GRP(can0_8),
> > > > > > +   DEFINE_ZYNQ_PINCTRL_GRP(can0_9),
> > > > > > +   DEFINE_ZYNQ_PINCTRL_GRP(can0_10),
> > > > > > +   DEFINE_ZYNQ_PINCTRL_GRP(can1_0),
> > > > > > +   DEFINE_ZYNQ_PINCTRL_GRP(can1_1),
> > > > > > +   DEFINE_ZYNQ_PINCTRL_GRP(can1_2),
> > > > > > +   DEFINE_ZYNQ_PINCTRL_GRP(can1_3),
> > > > > > +   DEFINE_ZYNQ_PINCTRL_GRP(can1_4),
> > > > > > +   DEFINE_ZYNQ_PINCTRL_GRP(can1_5),
> > > > > > +   DEFINE_ZYNQ_PINCTRL_GRP(can1_6),
> > > > > > +   DEFINE_ZYNQ_PINCTRL_GRP(can1_7),
> > > > > > +   DEFINE_ZYNQ_PINCTRL_GRP(can1_8),
> > > > > > +   DEFINE_ZYNQ_PINCTRL_GRP(can1_9),
> > > > > > +   DEFINE_ZYNQ_PINCTRL_GRP(can1_10),
> > > > > > +   DEFINE_ZYNQ_PINCTRL_GRP(can1_11),
> > > > > > +   DEFINE_ZYNQ_PINCTRL_GRP(uart0_0),
> > > > > > +   DEFINE_ZYNQ_PINCTRL_GRP(uart0_1),
> > > > > > +   DEFINE_ZYNQ_PINCTRL_GRP(uart0_2),
> > > > > > +   DEFINE_ZYNQ_PINCTRL_GRP(uart0_3),
> > > > > > +   DEFINE_ZYNQ_PINCTRL_GRP(uart0_4),
> > > > > > +   DEFINE_ZYNQ_PINCTRL_GRP(uart0_5),
> > > > > > +   DEFINE_ZYNQ_PINCTRL_GRP(uart0_6),
> > > > > > +   DEFINE_ZYNQ_PINCTRL_GRP(uart0_7),
> > > > > > +   DEFINE_ZYNQ_PINCTRL_GRP(uart0_8),
> > > > > > +   DEFINE_ZYNQ_PINCTRL_GRP(uart0_9),
> > > > > > +   DEFINE_ZYNQ_PINCTRL_GRP(uart0_10),
> > > > > > +   DEFINE_ZYNQ_PINCTRL_GRP(uart1_0),
> > > > > > +   DEFINE_ZYNQ_PINCTRL_GRP(uart1_1),
> > > > > > +   DEFINE_ZYNQ_PINCTRL_GRP(uart1_2),
> > > > > > +   DEFINE_ZYNQ_PINCTRL_GRP(uart1_3),
> > > > > > +   DEFINE_ZYNQ_PINCTRL_GRP(uart1_4),
> > > > > > +   DEFINE_ZYNQ_PINCTRL_GRP(uart1_5),
> > > > > > +   DEFINE_ZYNQ_PINCTRL_GRP(uart1_6),
> > > > > > +   DEFINE_ZYNQ_PINCTRL_GRP(uart1_7),
> > > > > > +   DEFINE_ZYNQ_PINCTRL_GRP(uart1_8),
> > > > > > +   DEFINE_ZYNQ_PINCTRL_GRP(uart1_9),
> > > > > > +   DEFINE_ZYNQ_PINCTRL_GRP(uart1_10),
> > > > > > +   DEFINE_ZYNQ_PINCTRL_GRP(uart1_11),
> > > > > > +   DEFINE_ZYNQ_PINCTRL_GRP(i2c0_0),
> > > > > > +   DEFINE_ZYNQ_PINCTRL_GRP(i2c0_1),
> > > > > > +   DEFINE_ZYNQ_PINCTRL_GRP(i2c0_2),
> > > > > > +   DEFINE_ZYNQ_PINCTRL_GRP(i2c0_3),
> > > > > > +

Re: [PATCH RFC v2 1/8] pinctrl: Add driver for Zynq

2014-11-02 Thread Sören Brinkmann 
On Thu, 2014-10-30 at 09:16AM +0100, Lothar Waßmann wrote:
 Hi,
 
 Sören Brinkmann wrote:
  On Wed, 2014-10-29 at 05:49AM +0100, Lothar Waßmann wrote:
   Hi,
   
   Sören Brinkmann wrote:
On Tue, 2014-10-28 at 04:16PM +0100, Lothar Waßmann wrote:
 Hi,
 
 Soren Brinkmann wrote:
  Signed-off-by: Soren Brinkmann soren.brinkm...@xilinx.com
  ---
  changes since RFC:
   - use syscon/regmap to access registers in SLCR space
   - add pinctrl to zc702 DT
   - rebase to 3.18: rename enable - set_mux
   - add kernel-doc
   - support pinconf
 - supported attributes
   - pin-bias: pull up, tristate, disable
   - slew-rate: 0 == slow, 1 == fast; generic pinconf does not 
  display
 argument
  
 [...]
  +struct zynq_pctrl_group zynq_pctrl_groups[] = {
  +   DEFINE_ZYNQ_PINCTRL_GRP(ethernet0_0),
  +   DEFINE_ZYNQ_PINCTRL_GRP(ethernet1_0),
  +   DEFINE_ZYNQ_PINCTRL_GRP(mdio0_0),
  +   DEFINE_ZYNQ_PINCTRL_GRP(mdio1_0),
  +   DEFINE_ZYNQ_PINCTRL_GRP(qspi0_0),
  +   DEFINE_ZYNQ_PINCTRL_GRP(qspi1_0),
  +   DEFINE_ZYNQ_PINCTRL_GRP(qspi_fbclk),
  +   DEFINE_ZYNQ_PINCTRL_GRP(qspi_cs1),
  +   DEFINE_ZYNQ_PINCTRL_GRP(spi0_0),
  +   DEFINE_ZYNQ_PINCTRL_GRP(spi0_1),
  +   DEFINE_ZYNQ_PINCTRL_GRP(spi0_2),
  +   DEFINE_ZYNQ_PINCTRL_GRP(spi1_0),
  +   DEFINE_ZYNQ_PINCTRL_GRP(spi1_1),
  +   DEFINE_ZYNQ_PINCTRL_GRP(spi1_2),
  +   DEFINE_ZYNQ_PINCTRL_GRP(spi1_3),
  +   DEFINE_ZYNQ_PINCTRL_GRP(sdio0_0),
  +   DEFINE_ZYNQ_PINCTRL_GRP(sdio0_1),
  +   DEFINE_ZYNQ_PINCTRL_GRP(sdio0_2),
  +   DEFINE_ZYNQ_PINCTRL_GRP(sdio1_0),
  +   DEFINE_ZYNQ_PINCTRL_GRP(sdio1_1),
  +   DEFINE_ZYNQ_PINCTRL_GRP(sdio1_2),
  +   DEFINE_ZYNQ_PINCTRL_GRP(sdio1_3),
  +   DEFINE_ZYNQ_PINCTRL_GRP(sdio0_emio_wp),
  +   DEFINE_ZYNQ_PINCTRL_GRP(sdio0_emio_cd),
  +   DEFINE_ZYNQ_PINCTRL_GRP(sdio1_emio_wp),
  +   DEFINE_ZYNQ_PINCTRL_GRP(sdio1_emio_cd),
  +   DEFINE_ZYNQ_PINCTRL_GRP(smc0_nor),
  +   DEFINE_ZYNQ_PINCTRL_GRP(smc0_nor_cs1),
  +   DEFINE_ZYNQ_PINCTRL_GRP(smc0_nor_addr25),
  +   DEFINE_ZYNQ_PINCTRL_GRP(smc0_nand),
  +   DEFINE_ZYNQ_PINCTRL_GRP(can0_0),
  +   DEFINE_ZYNQ_PINCTRL_GRP(can0_1),
  +   DEFINE_ZYNQ_PINCTRL_GRP(can0_2),
  +   DEFINE_ZYNQ_PINCTRL_GRP(can0_3),
  +   DEFINE_ZYNQ_PINCTRL_GRP(can0_4),
  +   DEFINE_ZYNQ_PINCTRL_GRP(can0_5),
  +   DEFINE_ZYNQ_PINCTRL_GRP(can0_6),
  +   DEFINE_ZYNQ_PINCTRL_GRP(can0_7),
  +   DEFINE_ZYNQ_PINCTRL_GRP(can0_8),
  +   DEFINE_ZYNQ_PINCTRL_GRP(can0_9),
  +   DEFINE_ZYNQ_PINCTRL_GRP(can0_10),
  +   DEFINE_ZYNQ_PINCTRL_GRP(can1_0),
  +   DEFINE_ZYNQ_PINCTRL_GRP(can1_1),
  +   DEFINE_ZYNQ_PINCTRL_GRP(can1_2),
  +   DEFINE_ZYNQ_PINCTRL_GRP(can1_3),
  +   DEFINE_ZYNQ_PINCTRL_GRP(can1_4),
  +   DEFINE_ZYNQ_PINCTRL_GRP(can1_5),
  +   DEFINE_ZYNQ_PINCTRL_GRP(can1_6),
  +   DEFINE_ZYNQ_PINCTRL_GRP(can1_7),
  +   DEFINE_ZYNQ_PINCTRL_GRP(can1_8),
  +   DEFINE_ZYNQ_PINCTRL_GRP(can1_9),
  +   DEFINE_ZYNQ_PINCTRL_GRP(can1_10),
  +   DEFINE_ZYNQ_PINCTRL_GRP(can1_11),
  +   DEFINE_ZYNQ_PINCTRL_GRP(uart0_0),
  +   DEFINE_ZYNQ_PINCTRL_GRP(uart0_1),
  +   DEFINE_ZYNQ_PINCTRL_GRP(uart0_2),
  +   DEFINE_ZYNQ_PINCTRL_GRP(uart0_3),
  +   DEFINE_ZYNQ_PINCTRL_GRP(uart0_4),
  +   DEFINE_ZYNQ_PINCTRL_GRP(uart0_5),
  +   DEFINE_ZYNQ_PINCTRL_GRP(uart0_6),
  +   DEFINE_ZYNQ_PINCTRL_GRP(uart0_7),
  +   DEFINE_ZYNQ_PINCTRL_GRP(uart0_8),
  +   DEFINE_ZYNQ_PINCTRL_GRP(uart0_9),
  +   DEFINE_ZYNQ_PINCTRL_GRP(uart0_10),
  +   DEFINE_ZYNQ_PINCTRL_GRP(uart1_0),
  +   DEFINE_ZYNQ_PINCTRL_GRP(uart1_1),
  +   DEFINE_ZYNQ_PINCTRL_GRP(uart1_2),
  +   DEFINE_ZYNQ_PINCTRL_GRP(uart1_3),
  +   DEFINE_ZYNQ_PINCTRL_GRP(uart1_4),
  +   DEFINE_ZYNQ_PINCTRL_GRP(uart1_5),
  +   DEFINE_ZYNQ_PINCTRL_GRP(uart1_6),
  +   DEFINE_ZYNQ_PINCTRL_GRP(uart1_7),
  +   DEFINE_ZYNQ_PINCTRL_GRP(uart1_8),
  +   DEFINE_ZYNQ_PINCTRL_GRP(uart1_9),
  +   DEFINE_ZYNQ_PINCTRL_GRP(uart1_10),
  +   DEFINE_ZYNQ_PINCTRL_GRP(uart1_11),
  +   DEFINE_ZYNQ_PINCTRL_GRP(i2c0_0),
  +   DEFINE_ZYNQ_PINCTRL_GRP(i2c0_1),
  +   DEFINE_ZYNQ_PINCTRL_GRP(i2c0_2),
  +   DEFINE_ZYNQ_PINCTRL_GRP(i2c0_3),
  +   DEFINE_ZYNQ_PINCTRL_GRP(i2c0_4),
  +   DEFINE_ZYNQ_PINCTRL_GRP(i2c0_5),
  +   DEFINE_ZYNQ_PINCTRL_GRP(i2c0_6),
  +   DEFINE_ZYNQ_PINCTRL_GRP(i2c0_7),
  +   DEFINE_ZYNQ_PINCTRL_GRP(i2c0_8),
  +   DEFINE_ZYNQ_PINCTRL_GRP(i2c0_9),
  +   DEFINE_ZYNQ_PINCTRL_GRP(i2c0_10),
  +   DEFINE_ZYNQ_PINCTRL_GRP(i2c1_0),
  +   DEFINE_ZYNQ_PINCTRL_GRP(i2c1_1),
  +   DEFINE_ZYNQ_PINCTRL_GRP(i2c1_2),
  +   DEFINE_ZYNQ_PINCTRL_GRP(i2c1_3),
  +   DEFINE_ZYNQ_PINCTRL_GRP(i2c1_4),
  +   DEFINE_ZYNQ_PINCTRL_GRP(i2c1_5),
  +   DEFINE_ZYNQ_PINCTRL_GRP(i2c1_6),

Re: [PATCH RFC v2 1/8] pinctrl: Add driver for Zynq

2014-10-30 Thread Lothar Waßmann 
Hi,

Sören Brinkmann wrote:
> On Wed, 2014-10-29 at 05:49AM +0100, Lothar Waßmann wrote:
> > Hi,
> > 
> > Sören Brinkmann wrote:
> > > On Tue, 2014-10-28 at 04:16PM +0100, Lothar Waßmann wrote:
> > > > Hi,
> > > > 
> > > > Soren Brinkmann wrote:
> > > > > Signed-off-by: Soren Brinkmann 
> > > > > ---
> > > > > changes since RFC:
> > > > >  - use syscon/regmap to access registers in SLCR space
> > > > >  - add pinctrl to zc702 DT
> > > > >  - rebase to 3.18: rename enable -> set_mux
> > > > >  - add kernel-doc
> > > > >  - support pinconf
> > > > >- supported attributes
> > > > >  - pin-bias: pull up, tristate, disable
> > > > >  - slew-rate: 0 == slow, 1 == fast; generic pinconf does not 
> > > > > display
> > > > >argument
> > > > > 
> > > > [...]
> > > > > +struct zynq_pctrl_group zynq_pctrl_groups[] = {
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(ethernet0_0),
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(ethernet1_0),
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(mdio0_0),
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(mdio1_0),
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(qspi0_0),
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(qspi1_0),
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(qspi_fbclk),
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(qspi_cs1),
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(spi0_0),
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(spi0_1),
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(spi0_2),
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(spi1_0),
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(spi1_1),
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(spi1_2),
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(spi1_3),
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(sdio0_0),
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(sdio0_1),
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(sdio0_2),
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(sdio1_0),
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(sdio1_1),
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(sdio1_2),
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(sdio1_3),
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(sdio0_emio_wp),
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(sdio0_emio_cd),
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(sdio1_emio_wp),
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(sdio1_emio_cd),
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(smc0_nor),
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(smc0_nor_cs1),
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(smc0_nor_addr25),
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(smc0_nand),
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(can0_0),
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(can0_1),
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(can0_2),
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(can0_3),
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(can0_4),
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(can0_5),
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(can0_6),
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(can0_7),
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(can0_8),
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(can0_9),
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(can0_10),
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(can1_0),
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(can1_1),
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(can1_2),
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(can1_3),
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(can1_4),
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(can1_5),
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(can1_6),
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(can1_7),
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(can1_8),
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(can1_9),
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(can1_10),
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(can1_11),
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(uart0_0),
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(uart0_1),
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(uart0_2),
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(uart0_3),
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(uart0_4),
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(uart0_5),
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(uart0_6),
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(uart0_7),
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(uart0_8),
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(uart0_9),
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(uart0_10),
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(uart1_0),
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(uart1_1),
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(uart1_2),
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(uart1_3),
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(uart1_4),
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(uart1_5),
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(uart1_6),
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(uart1_7),
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(uart1_8),
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(uart1_9),
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(uart1_10),
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(uart1_11),
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(i2c0_0),
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(i2c0_1),
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(i2c0_2),
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(i2c0_3),
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(i2c0_4),
> > > > > + DEFINE_ZYNQ_PINCTRL_GRP(i2c0_5),
> > > > > +

Re: [PATCH RFC v2 1/8] pinctrl: Add driver for Zynq

2014-10-30 Thread Lothar Waßmann 
Hi,

Sören Brinkmann wrote:
 On Wed, 2014-10-29 at 05:49AM +0100, Lothar Waßmann wrote:
  Hi,
  
  Sören Brinkmann wrote:
   On Tue, 2014-10-28 at 04:16PM +0100, Lothar Waßmann wrote:
Hi,

Soren Brinkmann wrote:
 Signed-off-by: Soren Brinkmann soren.brinkm...@xilinx.com
 ---
 changes since RFC:
  - use syscon/regmap to access registers in SLCR space
  - add pinctrl to zc702 DT
  - rebase to 3.18: rename enable - set_mux
  - add kernel-doc
  - support pinconf
- supported attributes
  - pin-bias: pull up, tristate, disable
  - slew-rate: 0 == slow, 1 == fast; generic pinconf does not 
 display
argument
 
[...]
 +struct zynq_pctrl_group zynq_pctrl_groups[] = {
 + DEFINE_ZYNQ_PINCTRL_GRP(ethernet0_0),
 + DEFINE_ZYNQ_PINCTRL_GRP(ethernet1_0),
 + DEFINE_ZYNQ_PINCTRL_GRP(mdio0_0),
 + DEFINE_ZYNQ_PINCTRL_GRP(mdio1_0),
 + DEFINE_ZYNQ_PINCTRL_GRP(qspi0_0),
 + DEFINE_ZYNQ_PINCTRL_GRP(qspi1_0),
 + DEFINE_ZYNQ_PINCTRL_GRP(qspi_fbclk),
 + DEFINE_ZYNQ_PINCTRL_GRP(qspi_cs1),
 + DEFINE_ZYNQ_PINCTRL_GRP(spi0_0),
 + DEFINE_ZYNQ_PINCTRL_GRP(spi0_1),
 + DEFINE_ZYNQ_PINCTRL_GRP(spi0_2),
 + DEFINE_ZYNQ_PINCTRL_GRP(spi1_0),
 + DEFINE_ZYNQ_PINCTRL_GRP(spi1_1),
 + DEFINE_ZYNQ_PINCTRL_GRP(spi1_2),
 + DEFINE_ZYNQ_PINCTRL_GRP(spi1_3),
 + DEFINE_ZYNQ_PINCTRL_GRP(sdio0_0),
 + DEFINE_ZYNQ_PINCTRL_GRP(sdio0_1),
 + DEFINE_ZYNQ_PINCTRL_GRP(sdio0_2),
 + DEFINE_ZYNQ_PINCTRL_GRP(sdio1_0),
 + DEFINE_ZYNQ_PINCTRL_GRP(sdio1_1),
 + DEFINE_ZYNQ_PINCTRL_GRP(sdio1_2),
 + DEFINE_ZYNQ_PINCTRL_GRP(sdio1_3),
 + DEFINE_ZYNQ_PINCTRL_GRP(sdio0_emio_wp),
 + DEFINE_ZYNQ_PINCTRL_GRP(sdio0_emio_cd),
 + DEFINE_ZYNQ_PINCTRL_GRP(sdio1_emio_wp),
 + DEFINE_ZYNQ_PINCTRL_GRP(sdio1_emio_cd),
 + DEFINE_ZYNQ_PINCTRL_GRP(smc0_nor),
 + DEFINE_ZYNQ_PINCTRL_GRP(smc0_nor_cs1),
 + DEFINE_ZYNQ_PINCTRL_GRP(smc0_nor_addr25),
 + DEFINE_ZYNQ_PINCTRL_GRP(smc0_nand),
 + DEFINE_ZYNQ_PINCTRL_GRP(can0_0),
 + DEFINE_ZYNQ_PINCTRL_GRP(can0_1),
 + DEFINE_ZYNQ_PINCTRL_GRP(can0_2),
 + DEFINE_ZYNQ_PINCTRL_GRP(can0_3),
 + DEFINE_ZYNQ_PINCTRL_GRP(can0_4),
 + DEFINE_ZYNQ_PINCTRL_GRP(can0_5),
 + DEFINE_ZYNQ_PINCTRL_GRP(can0_6),
 + DEFINE_ZYNQ_PINCTRL_GRP(can0_7),
 + DEFINE_ZYNQ_PINCTRL_GRP(can0_8),
 + DEFINE_ZYNQ_PINCTRL_GRP(can0_9),
 + DEFINE_ZYNQ_PINCTRL_GRP(can0_10),
 + DEFINE_ZYNQ_PINCTRL_GRP(can1_0),
 + DEFINE_ZYNQ_PINCTRL_GRP(can1_1),
 + DEFINE_ZYNQ_PINCTRL_GRP(can1_2),
 + DEFINE_ZYNQ_PINCTRL_GRP(can1_3),
 + DEFINE_ZYNQ_PINCTRL_GRP(can1_4),
 + DEFINE_ZYNQ_PINCTRL_GRP(can1_5),
 + DEFINE_ZYNQ_PINCTRL_GRP(can1_6),
 + DEFINE_ZYNQ_PINCTRL_GRP(can1_7),
 + DEFINE_ZYNQ_PINCTRL_GRP(can1_8),
 + DEFINE_ZYNQ_PINCTRL_GRP(can1_9),
 + DEFINE_ZYNQ_PINCTRL_GRP(can1_10),
 + DEFINE_ZYNQ_PINCTRL_GRP(can1_11),
 + DEFINE_ZYNQ_PINCTRL_GRP(uart0_0),
 + DEFINE_ZYNQ_PINCTRL_GRP(uart0_1),
 + DEFINE_ZYNQ_PINCTRL_GRP(uart0_2),
 + DEFINE_ZYNQ_PINCTRL_GRP(uart0_3),
 + DEFINE_ZYNQ_PINCTRL_GRP(uart0_4),
 + DEFINE_ZYNQ_PINCTRL_GRP(uart0_5),
 + DEFINE_ZYNQ_PINCTRL_GRP(uart0_6),
 + DEFINE_ZYNQ_PINCTRL_GRP(uart0_7),
 + DEFINE_ZYNQ_PINCTRL_GRP(uart0_8),
 + DEFINE_ZYNQ_PINCTRL_GRP(uart0_9),
 + DEFINE_ZYNQ_PINCTRL_GRP(uart0_10),
 + DEFINE_ZYNQ_PINCTRL_GRP(uart1_0),
 + DEFINE_ZYNQ_PINCTRL_GRP(uart1_1),
 + DEFINE_ZYNQ_PINCTRL_GRP(uart1_2),
 + DEFINE_ZYNQ_PINCTRL_GRP(uart1_3),
 + DEFINE_ZYNQ_PINCTRL_GRP(uart1_4),
 + DEFINE_ZYNQ_PINCTRL_GRP(uart1_5),
 + DEFINE_ZYNQ_PINCTRL_GRP(uart1_6),
 + DEFINE_ZYNQ_PINCTRL_GRP(uart1_7),
 + DEFINE_ZYNQ_PINCTRL_GRP(uart1_8),
 + DEFINE_ZYNQ_PINCTRL_GRP(uart1_9),
 + DEFINE_ZYNQ_PINCTRL_GRP(uart1_10),
 + DEFINE_ZYNQ_PINCTRL_GRP(uart1_11),
 + DEFINE_ZYNQ_PINCTRL_GRP(i2c0_0),
 + DEFINE_ZYNQ_PINCTRL_GRP(i2c0_1),
 + DEFINE_ZYNQ_PINCTRL_GRP(i2c0_2),
 + DEFINE_ZYNQ_PINCTRL_GRP(i2c0_3),
 + DEFINE_ZYNQ_PINCTRL_GRP(i2c0_4),
 + DEFINE_ZYNQ_PINCTRL_GRP(i2c0_5),
 + DEFINE_ZYNQ_PINCTRL_GRP(i2c0_6),
 + DEFINE_ZYNQ_PINCTRL_GRP(i2c0_7),
 + DEFINE_ZYNQ_PINCTRL_GRP(i2c0_8),
 + DEFINE_ZYNQ_PINCTRL_GRP(i2c0_9),
 + DEFINE_ZYNQ_PINCTRL_GRP(i2c0_10),
 + DEFINE_ZYNQ_PINCTRL_GRP(i2c1_0),
 + DEFINE_ZYNQ_PINCTRL_GRP(i2c1_1),
 + DEFINE_ZYNQ_PINCTRL_GRP(i2c1_2),
 + DEFINE_ZYNQ_PINCTRL_GRP(i2c1_3),
 + DEFINE_ZYNQ_PINCTRL_GRP(i2c1_4),
 + DEFINE_ZYNQ_PINCTRL_GRP(i2c1_5),
 +

Re: [PATCH RFC v2 1/8] pinctrl: Add driver for Zynq

2014-10-29 Thread Sören Brinkmann 
On Wed, 2014-10-29 at 05:49AM +0100, Lothar Waßmann wrote:
> Hi,
> 
> Sören Brinkmann wrote:
> > On Tue, 2014-10-28 at 04:16PM +0100, Lothar Waßmann wrote:
> > > Hi,
> > > 
> > > Soren Brinkmann wrote:
> > > > Signed-off-by: Soren Brinkmann 
> > > > ---
> > > > changes since RFC:
> > > >  - use syscon/regmap to access registers in SLCR space
> > > >  - add pinctrl to zc702 DT
> > > >  - rebase to 3.18: rename enable -> set_mux
> > > >  - add kernel-doc
> > > >  - support pinconf
> > > >- supported attributes
> > > >  - pin-bias: pull up, tristate, disable
> > > >  - slew-rate: 0 == slow, 1 == fast; generic pinconf does not display
> > > >argument
> > > > 
> > > [...]
> > > > +struct zynq_pctrl_group zynq_pctrl_groups[] = {
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(ethernet0_0),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(ethernet1_0),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(mdio0_0),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(mdio1_0),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(qspi0_0),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(qspi1_0),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(qspi_fbclk),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(qspi_cs1),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(spi0_0),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(spi0_1),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(spi0_2),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(spi1_0),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(spi1_1),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(spi1_2),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(spi1_3),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(sdio0_0),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(sdio0_1),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(sdio0_2),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(sdio1_0),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(sdio1_1),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(sdio1_2),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(sdio1_3),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(sdio0_emio_wp),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(sdio0_emio_cd),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(sdio1_emio_wp),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(sdio1_emio_cd),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(smc0_nor),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(smc0_nor_cs1),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(smc0_nor_addr25),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(smc0_nand),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(can0_0),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(can0_1),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(can0_2),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(can0_3),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(can0_4),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(can0_5),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(can0_6),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(can0_7),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(can0_8),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(can0_9),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(can0_10),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(can1_0),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(can1_1),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(can1_2),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(can1_3),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(can1_4),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(can1_5),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(can1_6),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(can1_7),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(can1_8),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(can1_9),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(can1_10),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(can1_11),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(uart0_0),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(uart0_1),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(uart0_2),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(uart0_3),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(uart0_4),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(uart0_5),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(uart0_6),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(uart0_7),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(uart0_8),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(uart0_9),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(uart0_10),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(uart1_0),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(uart1_1),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(uart1_2),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(uart1_3),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(uart1_4),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(uart1_5),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(uart1_6),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(uart1_7),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(uart1_8),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(uart1_9),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(uart1_10),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(uart1_11),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(i2c0_0),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(i2c0_1),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(i2c0_2),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(i2c0_3),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(i2c0_4),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(i2c0_5),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(i2c0_6),
> > > > +   DEFINE_ZYNQ_PINCTRL_GRP(i2c0_7),
> > > > +

Re: [PATCH RFC v2 1/8] pinctrl: Add driver for Zynq

2014-10-29 Thread Sören Brinkmann 
On Wed, 2014-10-29 at 05:49AM +0100, Lothar Waßmann wrote:
 Hi,
 
 Sören Brinkmann wrote:
  On Tue, 2014-10-28 at 04:16PM +0100, Lothar Waßmann wrote:
   Hi,
   
   Soren Brinkmann wrote:
Signed-off-by: Soren Brinkmann soren.brinkm...@xilinx.com
---
changes since RFC:
 - use syscon/regmap to access registers in SLCR space
 - add pinctrl to zc702 DT
 - rebase to 3.18: rename enable - set_mux
 - add kernel-doc
 - support pinconf
   - supported attributes
 - pin-bias: pull up, tristate, disable
 - slew-rate: 0 == slow, 1 == fast; generic pinconf does not display
   argument

   [...]
+struct zynq_pctrl_group zynq_pctrl_groups[] = {
+   DEFINE_ZYNQ_PINCTRL_GRP(ethernet0_0),
+   DEFINE_ZYNQ_PINCTRL_GRP(ethernet1_0),
+   DEFINE_ZYNQ_PINCTRL_GRP(mdio0_0),
+   DEFINE_ZYNQ_PINCTRL_GRP(mdio1_0),
+   DEFINE_ZYNQ_PINCTRL_GRP(qspi0_0),
+   DEFINE_ZYNQ_PINCTRL_GRP(qspi1_0),
+   DEFINE_ZYNQ_PINCTRL_GRP(qspi_fbclk),
+   DEFINE_ZYNQ_PINCTRL_GRP(qspi_cs1),
+   DEFINE_ZYNQ_PINCTRL_GRP(spi0_0),
+   DEFINE_ZYNQ_PINCTRL_GRP(spi0_1),
+   DEFINE_ZYNQ_PINCTRL_GRP(spi0_2),
+   DEFINE_ZYNQ_PINCTRL_GRP(spi1_0),
+   DEFINE_ZYNQ_PINCTRL_GRP(spi1_1),
+   DEFINE_ZYNQ_PINCTRL_GRP(spi1_2),
+   DEFINE_ZYNQ_PINCTRL_GRP(spi1_3),
+   DEFINE_ZYNQ_PINCTRL_GRP(sdio0_0),
+   DEFINE_ZYNQ_PINCTRL_GRP(sdio0_1),
+   DEFINE_ZYNQ_PINCTRL_GRP(sdio0_2),
+   DEFINE_ZYNQ_PINCTRL_GRP(sdio1_0),
+   DEFINE_ZYNQ_PINCTRL_GRP(sdio1_1),
+   DEFINE_ZYNQ_PINCTRL_GRP(sdio1_2),
+   DEFINE_ZYNQ_PINCTRL_GRP(sdio1_3),
+   DEFINE_ZYNQ_PINCTRL_GRP(sdio0_emio_wp),
+   DEFINE_ZYNQ_PINCTRL_GRP(sdio0_emio_cd),
+   DEFINE_ZYNQ_PINCTRL_GRP(sdio1_emio_wp),
+   DEFINE_ZYNQ_PINCTRL_GRP(sdio1_emio_cd),
+   DEFINE_ZYNQ_PINCTRL_GRP(smc0_nor),
+   DEFINE_ZYNQ_PINCTRL_GRP(smc0_nor_cs1),
+   DEFINE_ZYNQ_PINCTRL_GRP(smc0_nor_addr25),
+   DEFINE_ZYNQ_PINCTRL_GRP(smc0_nand),
+   DEFINE_ZYNQ_PINCTRL_GRP(can0_0),
+   DEFINE_ZYNQ_PINCTRL_GRP(can0_1),
+   DEFINE_ZYNQ_PINCTRL_GRP(can0_2),
+   DEFINE_ZYNQ_PINCTRL_GRP(can0_3),
+   DEFINE_ZYNQ_PINCTRL_GRP(can0_4),
+   DEFINE_ZYNQ_PINCTRL_GRP(can0_5),
+   DEFINE_ZYNQ_PINCTRL_GRP(can0_6),
+   DEFINE_ZYNQ_PINCTRL_GRP(can0_7),
+   DEFINE_ZYNQ_PINCTRL_GRP(can0_8),
+   DEFINE_ZYNQ_PINCTRL_GRP(can0_9),
+   DEFINE_ZYNQ_PINCTRL_GRP(can0_10),
+   DEFINE_ZYNQ_PINCTRL_GRP(can1_0),
+   DEFINE_ZYNQ_PINCTRL_GRP(can1_1),
+   DEFINE_ZYNQ_PINCTRL_GRP(can1_2),
+   DEFINE_ZYNQ_PINCTRL_GRP(can1_3),
+   DEFINE_ZYNQ_PINCTRL_GRP(can1_4),
+   DEFINE_ZYNQ_PINCTRL_GRP(can1_5),
+   DEFINE_ZYNQ_PINCTRL_GRP(can1_6),
+   DEFINE_ZYNQ_PINCTRL_GRP(can1_7),
+   DEFINE_ZYNQ_PINCTRL_GRP(can1_8),
+   DEFINE_ZYNQ_PINCTRL_GRP(can1_9),
+   DEFINE_ZYNQ_PINCTRL_GRP(can1_10),
+   DEFINE_ZYNQ_PINCTRL_GRP(can1_11),
+   DEFINE_ZYNQ_PINCTRL_GRP(uart0_0),
+   DEFINE_ZYNQ_PINCTRL_GRP(uart0_1),
+   DEFINE_ZYNQ_PINCTRL_GRP(uart0_2),
+   DEFINE_ZYNQ_PINCTRL_GRP(uart0_3),
+   DEFINE_ZYNQ_PINCTRL_GRP(uart0_4),
+   DEFINE_ZYNQ_PINCTRL_GRP(uart0_5),
+   DEFINE_ZYNQ_PINCTRL_GRP(uart0_6),
+   DEFINE_ZYNQ_PINCTRL_GRP(uart0_7),
+   DEFINE_ZYNQ_PINCTRL_GRP(uart0_8),
+   DEFINE_ZYNQ_PINCTRL_GRP(uart0_9),
+   DEFINE_ZYNQ_PINCTRL_GRP(uart0_10),
+   DEFINE_ZYNQ_PINCTRL_GRP(uart1_0),
+   DEFINE_ZYNQ_PINCTRL_GRP(uart1_1),
+   DEFINE_ZYNQ_PINCTRL_GRP(uart1_2),
+   DEFINE_ZYNQ_PINCTRL_GRP(uart1_3),
+   DEFINE_ZYNQ_PINCTRL_GRP(uart1_4),
+   DEFINE_ZYNQ_PINCTRL_GRP(uart1_5),
+   DEFINE_ZYNQ_PINCTRL_GRP(uart1_6),
+   DEFINE_ZYNQ_PINCTRL_GRP(uart1_7),
+   DEFINE_ZYNQ_PINCTRL_GRP(uart1_8),
+   DEFINE_ZYNQ_PINCTRL_GRP(uart1_9),
+   DEFINE_ZYNQ_PINCTRL_GRP(uart1_10),
+   DEFINE_ZYNQ_PINCTRL_GRP(uart1_11),
+   DEFINE_ZYNQ_PINCTRL_GRP(i2c0_0),
+   DEFINE_ZYNQ_PINCTRL_GRP(i2c0_1),
+   DEFINE_ZYNQ_PINCTRL_GRP(i2c0_2),
+   DEFINE_ZYNQ_PINCTRL_GRP(i2c0_3),
+   DEFINE_ZYNQ_PINCTRL_GRP(i2c0_4),
+   DEFINE_ZYNQ_PINCTRL_GRP(i2c0_5),
+   DEFINE_ZYNQ_PINCTRL_GRP(i2c0_6),
+   DEFINE_ZYNQ_PINCTRL_GRP(i2c0_7),
+   DEFINE_ZYNQ_PINCTRL_GRP(i2c0_8),
+   DEFINE_ZYNQ_PINCTRL_GRP(i2c0_9),
+   DEFINE_ZYNQ_PINCTRL_GRP(i2c0_10),
+   DEFINE_ZYNQ_PINCTRL_GRP(i2c1_0),
+   DEFINE_ZYNQ_PINCTRL_GRP(i2c1_1),
+   DEFINE_ZYNQ_PINCTRL_GRP(i2c1_2),
+   DEFINE_ZYNQ_PINCTRL_GRP(i2c1_3),
+   DEFINE_ZYNQ_PINCTRL_GRP(i2c1_4),
+   DEFINE_ZYNQ_PINCTRL_GRP(i2c1_5),

Re: [PATCH RFC v2 1/8] pinctrl: Add driver for Zynq

2014-10-28 Thread Lothar Waßmann 
Hi,

Sören Brinkmann wrote:
> On Tue, 2014-10-28 at 04:16PM +0100, Lothar Waßmann wrote:
> > Hi,
> > 
> > Soren Brinkmann wrote:
> > > Signed-off-by: Soren Brinkmann 
> > > ---
> > > changes since RFC:
> > >  - use syscon/regmap to access registers in SLCR space
> > >  - add pinctrl to zc702 DT
> > >  - rebase to 3.18: rename enable -> set_mux
> > >  - add kernel-doc
> > >  - support pinconf
> > >- supported attributes
> > >  - pin-bias: pull up, tristate, disable
> > >  - slew-rate: 0 == slow, 1 == fast; generic pinconf does not display
> > >argument
> > > 
> > [...]
> > > +struct zynq_pctrl_group zynq_pctrl_groups[] = {
> > > + DEFINE_ZYNQ_PINCTRL_GRP(ethernet0_0),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(ethernet1_0),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(mdio0_0),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(mdio1_0),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(qspi0_0),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(qspi1_0),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(qspi_fbclk),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(qspi_cs1),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(spi0_0),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(spi0_1),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(spi0_2),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(spi1_0),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(spi1_1),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(spi1_2),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(spi1_3),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(sdio0_0),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(sdio0_1),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(sdio0_2),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(sdio1_0),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(sdio1_1),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(sdio1_2),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(sdio1_3),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(sdio0_emio_wp),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(sdio0_emio_cd),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(sdio1_emio_wp),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(sdio1_emio_cd),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(smc0_nor),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(smc0_nor_cs1),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(smc0_nor_addr25),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(smc0_nand),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(can0_0),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(can0_1),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(can0_2),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(can0_3),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(can0_4),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(can0_5),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(can0_6),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(can0_7),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(can0_8),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(can0_9),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(can0_10),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(can1_0),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(can1_1),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(can1_2),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(can1_3),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(can1_4),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(can1_5),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(can1_6),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(can1_7),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(can1_8),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(can1_9),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(can1_10),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(can1_11),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(uart0_0),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(uart0_1),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(uart0_2),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(uart0_3),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(uart0_4),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(uart0_5),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(uart0_6),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(uart0_7),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(uart0_8),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(uart0_9),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(uart0_10),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(uart1_0),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(uart1_1),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(uart1_2),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(uart1_3),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(uart1_4),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(uart1_5),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(uart1_6),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(uart1_7),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(uart1_8),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(uart1_9),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(uart1_10),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(uart1_11),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(i2c0_0),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(i2c0_1),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(i2c0_2),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(i2c0_3),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(i2c0_4),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(i2c0_5),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(i2c0_6),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(i2c0_7),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(i2c0_8),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(i2c0_9),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(i2c0_10),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(i2c1_0),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(i2c1_1),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(i2c1_2),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(i2c1_3),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(i2c1_4),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(i2c1_5),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(i2c1_6),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(i2c1_7),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(i2c1_8),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(i2c1_9),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(i2c1_10),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(ttc0_0),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(ttc0_1),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(ttc0_2),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(ttc1_0),
> > > + DEFINE_ZYNQ_PINCTRL_GRP(ttc1_1),
> > > +

Re: [PATCH RFC v2 1/8] pinctrl: Add driver for Zynq

2014-10-28 Thread Sören Brinkmann 
On Tue, 2014-10-28 at 04:16PM +0100, Lothar Waßmann wrote:
> Hi,
> 
> Soren Brinkmann wrote:
> > Signed-off-by: Soren Brinkmann 
> > ---
> > changes since RFC:
> >  - use syscon/regmap to access registers in SLCR space
> >  - add pinctrl to zc702 DT
> >  - rebase to 3.18: rename enable -> set_mux
> >  - add kernel-doc
> >  - support pinconf
> >- supported attributes
> >  - pin-bias: pull up, tristate, disable
> >  - slew-rate: 0 == slow, 1 == fast; generic pinconf does not display
> >argument
> > 
> [...]
> > +struct zynq_pctrl_group zynq_pctrl_groups[] = {
> > +   DEFINE_ZYNQ_PINCTRL_GRP(ethernet0_0),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(ethernet1_0),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(mdio0_0),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(mdio1_0),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(qspi0_0),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(qspi1_0),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(qspi_fbclk),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(qspi_cs1),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(spi0_0),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(spi0_1),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(spi0_2),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(spi1_0),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(spi1_1),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(spi1_2),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(spi1_3),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(sdio0_0),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(sdio0_1),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(sdio0_2),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(sdio1_0),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(sdio1_1),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(sdio1_2),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(sdio1_3),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(sdio0_emio_wp),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(sdio0_emio_cd),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(sdio1_emio_wp),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(sdio1_emio_cd),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(smc0_nor),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(smc0_nor_cs1),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(smc0_nor_addr25),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(smc0_nand),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(can0_0),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(can0_1),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(can0_2),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(can0_3),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(can0_4),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(can0_5),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(can0_6),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(can0_7),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(can0_8),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(can0_9),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(can0_10),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(can1_0),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(can1_1),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(can1_2),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(can1_3),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(can1_4),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(can1_5),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(can1_6),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(can1_7),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(can1_8),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(can1_9),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(can1_10),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(can1_11),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(uart0_0),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(uart0_1),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(uart0_2),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(uart0_3),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(uart0_4),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(uart0_5),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(uart0_6),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(uart0_7),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(uart0_8),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(uart0_9),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(uart0_10),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(uart1_0),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(uart1_1),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(uart1_2),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(uart1_3),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(uart1_4),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(uart1_5),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(uart1_6),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(uart1_7),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(uart1_8),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(uart1_9),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(uart1_10),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(uart1_11),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(i2c0_0),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(i2c0_1),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(i2c0_2),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(i2c0_3),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(i2c0_4),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(i2c0_5),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(i2c0_6),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(i2c0_7),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(i2c0_8),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(i2c0_9),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(i2c0_10),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(i2c1_0),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(i2c1_1),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(i2c1_2),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(i2c1_3),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(i2c1_4),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(i2c1_5),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(i2c1_6),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(i2c1_7),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(i2c1_8),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(i2c1_9),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(i2c1_10),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(ttc0_0),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(ttc0_1),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(ttc0_2),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(ttc1_0),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(ttc1_1),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(ttc1_2),
> > +   DEFINE_ZYNQ_PINCTRL_GRP(swdt0_0),
>

Re: [PATCH RFC v2 1/8] pinctrl: Add driver for Zynq

2014-10-28 Thread Sören Brinkmann 
On Tue, 2014-10-28 at 03:53PM +0100, Linus Walleij wrote:
> On Thu, Oct 16, 2014 at 7:11 PM, Soren Brinkmann
>  wrote:
> 
> > Signed-off-by: Soren Brinkmann 
> > ---
> > changes since RFC:
> >  - use syscon/regmap to access registers in SLCR space
> >  - add pinctrl to zc702 DT
> >  - rebase to 3.18: rename enable -> set_mux
> >  - add kernel-doc
> >  - support pinconf
> >- supported attributes
> >  - pin-bias: pull up, tristate, disable
> >  - slew-rate: 0 == slow, 1 == fast; generic pinconf does not display
> >argument
> 
> Great progress!!

Thans.

> 
> (...)
> > +++ b/arch/arm/mach-zynq/Kconfig
> > @@ -9,6 +9,7 @@ config ARCH_ZYNQ
> > select HAVE_ARM_TWD if SMP
> > select ICST
> > select MFD_SYSCON
> > +   select PINCTRL
> 
> Don't you also want to select PINCTRL_ZYNQ or is it
> really optional?

Yep, you're right. I did some testing and it is required. I already have
that included in my work tree.

> 
> > select SOC_BUS
> > help
> >   Support for Xilinx Zynq ARM Cortex A9 Platform
> 
> Please split these machine changes into a separate patch. It is hitting
> a totally different subsystem.

OK

> 
> (...)
> > +++ b/drivers/pinctrl/pinctrl-zynq.c
> (...)
> > +static const struct pinctrl_ops zynq_pctrl_ops = {
> > +   .get_groups_count = zynq_pctrl_get_groups_count,
> > +   .get_group_name = zynq_pctrl_get_group_name,
> > +   .get_group_pins = zynq_pctrl_get_group_pins,
> > +   .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
> > +   .dt_free_map = pinctrl_utils_dt_free_map
> > +};
> 
> Nice use of generic functions!

Yeah, but for it to really work I need the changes I made to
pinconf-generic. Otherwise things just don't work well since I would
only be able to either select pin groups or pins in DT.

> 
> > +static int zynq_pinconf_cfg_get(struct pinctrl_dev *pctldev,
> > +   unsigned pin,
> > +   unsigned long *config)
> > +{
> > +   u32 reg;
> > +   int ret;
> > +   unsigned int arg = 0;
> > +   unsigned int param = pinconf_to_config_param(*config);
> > +   struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
> > +
> > +   if (pin > 53)
> > +   return -ENOTSUPP;
> 
> 53 looks a bit magical? #define or comment here to explain what's
> going on?

Yep, I'll add something like ZYNQ_NUM_MIOS

> 
> Apart from these small things this looks like merge material.

That is good to hear, thank you. But before merging this the
pinconf-generic changes need to go through. Even though I didn't order
things that way in this series (I wanted to show how my work proceeded),
proper operation depends of the driver depends on those pinconf-generic
changes.

Thanks,
Sören
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Re: [PATCH RFC v2 1/8] pinctrl: Add driver for Zynq

2014-10-28 Thread Lothar Waßmann 
Hi,

Soren Brinkmann wrote:
> Signed-off-by: Soren Brinkmann 
> ---
> changes since RFC:
>  - use syscon/regmap to access registers in SLCR space
>  - add pinctrl to zc702 DT
>  - rebase to 3.18: rename enable -> set_mux
>  - add kernel-doc
>  - support pinconf
>- supported attributes
>  - pin-bias: pull up, tristate, disable
>  - slew-rate: 0 == slow, 1 == fast; generic pinconf does not display
>argument
> 
[...]
> +struct zynq_pctrl_group zynq_pctrl_groups[] = {
> + DEFINE_ZYNQ_PINCTRL_GRP(ethernet0_0),
> + DEFINE_ZYNQ_PINCTRL_GRP(ethernet1_0),
> + DEFINE_ZYNQ_PINCTRL_GRP(mdio0_0),
> + DEFINE_ZYNQ_PINCTRL_GRP(mdio1_0),
> + DEFINE_ZYNQ_PINCTRL_GRP(qspi0_0),
> + DEFINE_ZYNQ_PINCTRL_GRP(qspi1_0),
> + DEFINE_ZYNQ_PINCTRL_GRP(qspi_fbclk),
> + DEFINE_ZYNQ_PINCTRL_GRP(qspi_cs1),
> + DEFINE_ZYNQ_PINCTRL_GRP(spi0_0),
> + DEFINE_ZYNQ_PINCTRL_GRP(spi0_1),
> + DEFINE_ZYNQ_PINCTRL_GRP(spi0_2),
> + DEFINE_ZYNQ_PINCTRL_GRP(spi1_0),
> + DEFINE_ZYNQ_PINCTRL_GRP(spi1_1),
> + DEFINE_ZYNQ_PINCTRL_GRP(spi1_2),
> + DEFINE_ZYNQ_PINCTRL_GRP(spi1_3),
> + DEFINE_ZYNQ_PINCTRL_GRP(sdio0_0),
> + DEFINE_ZYNQ_PINCTRL_GRP(sdio0_1),
> + DEFINE_ZYNQ_PINCTRL_GRP(sdio0_2),
> + DEFINE_ZYNQ_PINCTRL_GRP(sdio1_0),
> + DEFINE_ZYNQ_PINCTRL_GRP(sdio1_1),
> + DEFINE_ZYNQ_PINCTRL_GRP(sdio1_2),
> + DEFINE_ZYNQ_PINCTRL_GRP(sdio1_3),
> + DEFINE_ZYNQ_PINCTRL_GRP(sdio0_emio_wp),
> + DEFINE_ZYNQ_PINCTRL_GRP(sdio0_emio_cd),
> + DEFINE_ZYNQ_PINCTRL_GRP(sdio1_emio_wp),
> + DEFINE_ZYNQ_PINCTRL_GRP(sdio1_emio_cd),
> + DEFINE_ZYNQ_PINCTRL_GRP(smc0_nor),
> + DEFINE_ZYNQ_PINCTRL_GRP(smc0_nor_cs1),
> + DEFINE_ZYNQ_PINCTRL_GRP(smc0_nor_addr25),
> + DEFINE_ZYNQ_PINCTRL_GRP(smc0_nand),
> + DEFINE_ZYNQ_PINCTRL_GRP(can0_0),
> + DEFINE_ZYNQ_PINCTRL_GRP(can0_1),
> + DEFINE_ZYNQ_PINCTRL_GRP(can0_2),
> + DEFINE_ZYNQ_PINCTRL_GRP(can0_3),
> + DEFINE_ZYNQ_PINCTRL_GRP(can0_4),
> + DEFINE_ZYNQ_PINCTRL_GRP(can0_5),
> + DEFINE_ZYNQ_PINCTRL_GRP(can0_6),
> + DEFINE_ZYNQ_PINCTRL_GRP(can0_7),
> + DEFINE_ZYNQ_PINCTRL_GRP(can0_8),
> + DEFINE_ZYNQ_PINCTRL_GRP(can0_9),
> + DEFINE_ZYNQ_PINCTRL_GRP(can0_10),
> + DEFINE_ZYNQ_PINCTRL_GRP(can1_0),
> + DEFINE_ZYNQ_PINCTRL_GRP(can1_1),
> + DEFINE_ZYNQ_PINCTRL_GRP(can1_2),
> + DEFINE_ZYNQ_PINCTRL_GRP(can1_3),
> + DEFINE_ZYNQ_PINCTRL_GRP(can1_4),
> + DEFINE_ZYNQ_PINCTRL_GRP(can1_5),
> + DEFINE_ZYNQ_PINCTRL_GRP(can1_6),
> + DEFINE_ZYNQ_PINCTRL_GRP(can1_7),
> + DEFINE_ZYNQ_PINCTRL_GRP(can1_8),
> + DEFINE_ZYNQ_PINCTRL_GRP(can1_9),
> + DEFINE_ZYNQ_PINCTRL_GRP(can1_10),
> + DEFINE_ZYNQ_PINCTRL_GRP(can1_11),
> + DEFINE_ZYNQ_PINCTRL_GRP(uart0_0),
> + DEFINE_ZYNQ_PINCTRL_GRP(uart0_1),
> + DEFINE_ZYNQ_PINCTRL_GRP(uart0_2),
> + DEFINE_ZYNQ_PINCTRL_GRP(uart0_3),
> + DEFINE_ZYNQ_PINCTRL_GRP(uart0_4),
> + DEFINE_ZYNQ_PINCTRL_GRP(uart0_5),
> + DEFINE_ZYNQ_PINCTRL_GRP(uart0_6),
> + DEFINE_ZYNQ_PINCTRL_GRP(uart0_7),
> + DEFINE_ZYNQ_PINCTRL_GRP(uart0_8),
> + DEFINE_ZYNQ_PINCTRL_GRP(uart0_9),
> + DEFINE_ZYNQ_PINCTRL_GRP(uart0_10),
> + DEFINE_ZYNQ_PINCTRL_GRP(uart1_0),
> + DEFINE_ZYNQ_PINCTRL_GRP(uart1_1),
> + DEFINE_ZYNQ_PINCTRL_GRP(uart1_2),
> + DEFINE_ZYNQ_PINCTRL_GRP(uart1_3),
> + DEFINE_ZYNQ_PINCTRL_GRP(uart1_4),
> + DEFINE_ZYNQ_PINCTRL_GRP(uart1_5),
> + DEFINE_ZYNQ_PINCTRL_GRP(uart1_6),
> + DEFINE_ZYNQ_PINCTRL_GRP(uart1_7),
> + DEFINE_ZYNQ_PINCTRL_GRP(uart1_8),
> + DEFINE_ZYNQ_PINCTRL_GRP(uart1_9),
> + DEFINE_ZYNQ_PINCTRL_GRP(uart1_10),
> + DEFINE_ZYNQ_PINCTRL_GRP(uart1_11),
> + DEFINE_ZYNQ_PINCTRL_GRP(i2c0_0),
> + DEFINE_ZYNQ_PINCTRL_GRP(i2c0_1),
> + DEFINE_ZYNQ_PINCTRL_GRP(i2c0_2),
> + DEFINE_ZYNQ_PINCTRL_GRP(i2c0_3),
> + DEFINE_ZYNQ_PINCTRL_GRP(i2c0_4),
> + DEFINE_ZYNQ_PINCTRL_GRP(i2c0_5),
> + DEFINE_ZYNQ_PINCTRL_GRP(i2c0_6),
> + DEFINE_ZYNQ_PINCTRL_GRP(i2c0_7),
> + DEFINE_ZYNQ_PINCTRL_GRP(i2c0_8),
> + DEFINE_ZYNQ_PINCTRL_GRP(i2c0_9),
> + DEFINE_ZYNQ_PINCTRL_GRP(i2c0_10),
> + DEFINE_ZYNQ_PINCTRL_GRP(i2c1_0),
> + DEFINE_ZYNQ_PINCTRL_GRP(i2c1_1),
> + DEFINE_ZYNQ_PINCTRL_GRP(i2c1_2),
> + DEFINE_ZYNQ_PINCTRL_GRP(i2c1_3),
> + DEFINE_ZYNQ_PINCTRL_GRP(i2c1_4),
> + DEFINE_ZYNQ_PINCTRL_GRP(i2c1_5),
> + DEFINE_ZYNQ_PINCTRL_GRP(i2c1_6),
> + DEFINE_ZYNQ_PINCTRL_GRP(i2c1_7),
> + DEFINE_ZYNQ_PINCTRL_GRP(i2c1_8),
> + DEFINE_ZYNQ_PINCTRL_GRP(i2c1_9),
> + DEFINE_ZYNQ_PINCTRL_GRP(i2c1_10),
> + DEFINE_ZYNQ_PINCTRL_GRP(ttc0_0),
> + DEFINE_ZYNQ_PINCTRL_GRP(ttc0_1),
> + DEFINE_ZYNQ_PINCTRL_GRP(ttc0_2),
> + DEFINE_ZYNQ_PINCTRL_GRP(ttc1_0),
> + DEFINE_ZYNQ_PINCTRL_GRP(ttc1_1),
> + DEFINE_ZYNQ_PINCTRL_GRP(ttc1_2),
> + DEFINE_ZYNQ_PINCTRL_GRP(swdt0_0),
> + DEFINE_ZYNQ_PINCTRL_GRP(swdt0_1),
> + DEFINE_ZYNQ_PINCTRL_GRP(swdt0_2),
> +

Re: [PATCH RFC v2 1/8] pinctrl: Add driver for Zynq

2014-10-28 Thread Linus Walleij 
On Thu, Oct 16, 2014 at 7:11 PM, Soren Brinkmann
 wrote:

> Signed-off-by: Soren Brinkmann 
> ---
> changes since RFC:
>  - use syscon/regmap to access registers in SLCR space
>  - add pinctrl to zc702 DT
>  - rebase to 3.18: rename enable -> set_mux
>  - add kernel-doc
>  - support pinconf
>- supported attributes
>  - pin-bias: pull up, tristate, disable
>  - slew-rate: 0 == slow, 1 == fast; generic pinconf does not display
>argument

Great progress!!

(...)
> +++ b/arch/arm/mach-zynq/Kconfig
> @@ -9,6 +9,7 @@ config ARCH_ZYNQ
> select HAVE_ARM_TWD if SMP
> select ICST
> select MFD_SYSCON
> +   select PINCTRL

Don't you also want to select PINCTRL_ZYNQ or is it
really optional?

> select SOC_BUS
> help
>   Support for Xilinx Zynq ARM Cortex A9 Platform

Please split these machine changes into a separate patch. It is hitting
a totally different subsystem.

(...)
> +++ b/drivers/pinctrl/pinctrl-zynq.c
(...)
> +static const struct pinctrl_ops zynq_pctrl_ops = {
> +   .get_groups_count = zynq_pctrl_get_groups_count,
> +   .get_group_name = zynq_pctrl_get_group_name,
> +   .get_group_pins = zynq_pctrl_get_group_pins,
> +   .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
> +   .dt_free_map = pinctrl_utils_dt_free_map
> +};

Nice use of generic functions!

> +static int zynq_pinconf_cfg_get(struct pinctrl_dev *pctldev,
> +   unsigned pin,
> +   unsigned long *config)
> +{
> +   u32 reg;
> +   int ret;
> +   unsigned int arg = 0;
> +   unsigned int param = pinconf_to_config_param(*config);
> +   struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
> +
> +   if (pin > 53)
> +   return -ENOTSUPP;

53 looks a bit magical? #define or comment here to explain what's
going on?

Apart from these small things this looks like merge material.

Yours,
Linus Walleij
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Re: [PATCH RFC v2 1/8] pinctrl: Add driver for Zynq

2014-10-28 Thread Linus Walleij 
On Thu, Oct 16, 2014 at 7:11 PM, Soren Brinkmann
soren.brinkm...@xilinx.com wrote:

 Signed-off-by: Soren Brinkmann soren.brinkm...@xilinx.com
 ---
 changes since RFC:
  - use syscon/regmap to access registers in SLCR space
  - add pinctrl to zc702 DT
  - rebase to 3.18: rename enable - set_mux
  - add kernel-doc
  - support pinconf
- supported attributes
  - pin-bias: pull up, tristate, disable
  - slew-rate: 0 == slow, 1 == fast; generic pinconf does not display
argument

Great progress!!

(...)
 +++ b/arch/arm/mach-zynq/Kconfig
 @@ -9,6 +9,7 @@ config ARCH_ZYNQ
 select HAVE_ARM_TWD if SMP
 select ICST
 select MFD_SYSCON
 +   select PINCTRL

Don't you also want to select PINCTRL_ZYNQ or is it
really optional?

 select SOC_BUS
 help
   Support for Xilinx Zynq ARM Cortex A9 Platform

Please split these machine changes into a separate patch. It is hitting
a totally different subsystem.

(...)
 +++ b/drivers/pinctrl/pinctrl-zynq.c
(...)
 +static const struct pinctrl_ops zynq_pctrl_ops = {
 +   .get_groups_count = zynq_pctrl_get_groups_count,
 +   .get_group_name = zynq_pctrl_get_group_name,
 +   .get_group_pins = zynq_pctrl_get_group_pins,
 +   .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
 +   .dt_free_map = pinctrl_utils_dt_free_map
 +};

Nice use of generic functions!

 +static int zynq_pinconf_cfg_get(struct pinctrl_dev *pctldev,
 +   unsigned pin,
 +   unsigned long *config)
 +{
 +   u32 reg;
 +   int ret;
 +   unsigned int arg = 0;
 +   unsigned int param = pinconf_to_config_param(*config);
 +   struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 +
 +   if (pin  53)
 +   return -ENOTSUPP;

53 looks a bit magical? #define or comment here to explain what's
going on?

Apart from these small things this looks like merge material.

Yours,
Linus Walleij
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Re: [PATCH RFC v2 1/8] pinctrl: Add driver for Zynq

2014-10-28 Thread Lothar Waßmann 
Hi,

Soren Brinkmann wrote:
 Signed-off-by: Soren Brinkmann soren.brinkm...@xilinx.com
 ---
 changes since RFC:
  - use syscon/regmap to access registers in SLCR space
  - add pinctrl to zc702 DT
  - rebase to 3.18: rename enable - set_mux
  - add kernel-doc
  - support pinconf
- supported attributes
  - pin-bias: pull up, tristate, disable
  - slew-rate: 0 == slow, 1 == fast; generic pinconf does not display
argument
 
[...]
 +struct zynq_pctrl_group zynq_pctrl_groups[] = {
 + DEFINE_ZYNQ_PINCTRL_GRP(ethernet0_0),
 + DEFINE_ZYNQ_PINCTRL_GRP(ethernet1_0),
 + DEFINE_ZYNQ_PINCTRL_GRP(mdio0_0),
 + DEFINE_ZYNQ_PINCTRL_GRP(mdio1_0),
 + DEFINE_ZYNQ_PINCTRL_GRP(qspi0_0),
 + DEFINE_ZYNQ_PINCTRL_GRP(qspi1_0),
 + DEFINE_ZYNQ_PINCTRL_GRP(qspi_fbclk),
 + DEFINE_ZYNQ_PINCTRL_GRP(qspi_cs1),
 + DEFINE_ZYNQ_PINCTRL_GRP(spi0_0),
 + DEFINE_ZYNQ_PINCTRL_GRP(spi0_1),
 + DEFINE_ZYNQ_PINCTRL_GRP(spi0_2),
 + DEFINE_ZYNQ_PINCTRL_GRP(spi1_0),
 + DEFINE_ZYNQ_PINCTRL_GRP(spi1_1),
 + DEFINE_ZYNQ_PINCTRL_GRP(spi1_2),
 + DEFINE_ZYNQ_PINCTRL_GRP(spi1_3),
 + DEFINE_ZYNQ_PINCTRL_GRP(sdio0_0),
 + DEFINE_ZYNQ_PINCTRL_GRP(sdio0_1),
 + DEFINE_ZYNQ_PINCTRL_GRP(sdio0_2),
 + DEFINE_ZYNQ_PINCTRL_GRP(sdio1_0),
 + DEFINE_ZYNQ_PINCTRL_GRP(sdio1_1),
 + DEFINE_ZYNQ_PINCTRL_GRP(sdio1_2),
 + DEFINE_ZYNQ_PINCTRL_GRP(sdio1_3),
 + DEFINE_ZYNQ_PINCTRL_GRP(sdio0_emio_wp),
 + DEFINE_ZYNQ_PINCTRL_GRP(sdio0_emio_cd),
 + DEFINE_ZYNQ_PINCTRL_GRP(sdio1_emio_wp),
 + DEFINE_ZYNQ_PINCTRL_GRP(sdio1_emio_cd),
 + DEFINE_ZYNQ_PINCTRL_GRP(smc0_nor),
 + DEFINE_ZYNQ_PINCTRL_GRP(smc0_nor_cs1),
 + DEFINE_ZYNQ_PINCTRL_GRP(smc0_nor_addr25),
 + DEFINE_ZYNQ_PINCTRL_GRP(smc0_nand),
 + DEFINE_ZYNQ_PINCTRL_GRP(can0_0),
 + DEFINE_ZYNQ_PINCTRL_GRP(can0_1),
 + DEFINE_ZYNQ_PINCTRL_GRP(can0_2),
 + DEFINE_ZYNQ_PINCTRL_GRP(can0_3),
 + DEFINE_ZYNQ_PINCTRL_GRP(can0_4),
 + DEFINE_ZYNQ_PINCTRL_GRP(can0_5),
 + DEFINE_ZYNQ_PINCTRL_GRP(can0_6),
 + DEFINE_ZYNQ_PINCTRL_GRP(can0_7),
 + DEFINE_ZYNQ_PINCTRL_GRP(can0_8),
 + DEFINE_ZYNQ_PINCTRL_GRP(can0_9),
 + DEFINE_ZYNQ_PINCTRL_GRP(can0_10),
 + DEFINE_ZYNQ_PINCTRL_GRP(can1_0),
 + DEFINE_ZYNQ_PINCTRL_GRP(can1_1),
 + DEFINE_ZYNQ_PINCTRL_GRP(can1_2),
 + DEFINE_ZYNQ_PINCTRL_GRP(can1_3),
 + DEFINE_ZYNQ_PINCTRL_GRP(can1_4),
 + DEFINE_ZYNQ_PINCTRL_GRP(can1_5),
 + DEFINE_ZYNQ_PINCTRL_GRP(can1_6),
 + DEFINE_ZYNQ_PINCTRL_GRP(can1_7),
 + DEFINE_ZYNQ_PINCTRL_GRP(can1_8),
 + DEFINE_ZYNQ_PINCTRL_GRP(can1_9),
 + DEFINE_ZYNQ_PINCTRL_GRP(can1_10),
 + DEFINE_ZYNQ_PINCTRL_GRP(can1_11),
 + DEFINE_ZYNQ_PINCTRL_GRP(uart0_0),
 + DEFINE_ZYNQ_PINCTRL_GRP(uart0_1),
 + DEFINE_ZYNQ_PINCTRL_GRP(uart0_2),
 + DEFINE_ZYNQ_PINCTRL_GRP(uart0_3),
 + DEFINE_ZYNQ_PINCTRL_GRP(uart0_4),
 + DEFINE_ZYNQ_PINCTRL_GRP(uart0_5),
 + DEFINE_ZYNQ_PINCTRL_GRP(uart0_6),
 + DEFINE_ZYNQ_PINCTRL_GRP(uart0_7),
 + DEFINE_ZYNQ_PINCTRL_GRP(uart0_8),
 + DEFINE_ZYNQ_PINCTRL_GRP(uart0_9),
 + DEFINE_ZYNQ_PINCTRL_GRP(uart0_10),
 + DEFINE_ZYNQ_PINCTRL_GRP(uart1_0),
 + DEFINE_ZYNQ_PINCTRL_GRP(uart1_1),
 + DEFINE_ZYNQ_PINCTRL_GRP(uart1_2),
 + DEFINE_ZYNQ_PINCTRL_GRP(uart1_3),
 + DEFINE_ZYNQ_PINCTRL_GRP(uart1_4),
 + DEFINE_ZYNQ_PINCTRL_GRP(uart1_5),
 + DEFINE_ZYNQ_PINCTRL_GRP(uart1_6),
 + DEFINE_ZYNQ_PINCTRL_GRP(uart1_7),
 + DEFINE_ZYNQ_PINCTRL_GRP(uart1_8),
 + DEFINE_ZYNQ_PINCTRL_GRP(uart1_9),
 + DEFINE_ZYNQ_PINCTRL_GRP(uart1_10),
 + DEFINE_ZYNQ_PINCTRL_GRP(uart1_11),
 + DEFINE_ZYNQ_PINCTRL_GRP(i2c0_0),
 + DEFINE_ZYNQ_PINCTRL_GRP(i2c0_1),
 + DEFINE_ZYNQ_PINCTRL_GRP(i2c0_2),
 + DEFINE_ZYNQ_PINCTRL_GRP(i2c0_3),
 + DEFINE_ZYNQ_PINCTRL_GRP(i2c0_4),
 + DEFINE_ZYNQ_PINCTRL_GRP(i2c0_5),
 + DEFINE_ZYNQ_PINCTRL_GRP(i2c0_6),
 + DEFINE_ZYNQ_PINCTRL_GRP(i2c0_7),
 + DEFINE_ZYNQ_PINCTRL_GRP(i2c0_8),
 + DEFINE_ZYNQ_PINCTRL_GRP(i2c0_9),
 + DEFINE_ZYNQ_PINCTRL_GRP(i2c0_10),
 + DEFINE_ZYNQ_PINCTRL_GRP(i2c1_0),
 + DEFINE_ZYNQ_PINCTRL_GRP(i2c1_1),
 + DEFINE_ZYNQ_PINCTRL_GRP(i2c1_2),
 + DEFINE_ZYNQ_PINCTRL_GRP(i2c1_3),
 + DEFINE_ZYNQ_PINCTRL_GRP(i2c1_4),
 + DEFINE_ZYNQ_PINCTRL_GRP(i2c1_5),
 + DEFINE_ZYNQ_PINCTRL_GRP(i2c1_6),
 + DEFINE_ZYNQ_PINCTRL_GRP(i2c1_7),
 + DEFINE_ZYNQ_PINCTRL_GRP(i2c1_8),
 + DEFINE_ZYNQ_PINCTRL_GRP(i2c1_9),
 + DEFINE_ZYNQ_PINCTRL_GRP(i2c1_10),
 + DEFINE_ZYNQ_PINCTRL_GRP(ttc0_0),
 + DEFINE_ZYNQ_PINCTRL_GRP(ttc0_1),
 + DEFINE_ZYNQ_PINCTRL_GRP(ttc0_2),
 + DEFINE_ZYNQ_PINCTRL_GRP(ttc1_0),
 + DEFINE_ZYNQ_PINCTRL_GRP(ttc1_1),
 + DEFINE_ZYNQ_PINCTRL_GRP(ttc1_2),
 + DEFINE_ZYNQ_PINCTRL_GRP(swdt0_0),
 + DEFINE_ZYNQ_PINCTRL_GRP(swdt0_1),
 + DEFINE_ZYNQ_PINCTRL_GRP(swdt0_2),
 + DEFINE_ZYNQ_PINCTRL_GRP(swdt0_3),
 + DEFINE_ZYNQ_PINCTRL_GRP(swdt0_4),
 +

Re: [PATCH RFC v2 1/8] pinctrl: Add driver for Zynq

2014-10-28 Thread Sören Brinkmann 
On Tue, 2014-10-28 at 03:53PM +0100, Linus Walleij wrote:
 On Thu, Oct 16, 2014 at 7:11 PM, Soren Brinkmann
 soren.brinkm...@xilinx.com wrote:
 
  Signed-off-by: Soren Brinkmann soren.brinkm...@xilinx.com
  ---
  changes since RFC:
   - use syscon/regmap to access registers in SLCR space
   - add pinctrl to zc702 DT
   - rebase to 3.18: rename enable - set_mux
   - add kernel-doc
   - support pinconf
 - supported attributes
   - pin-bias: pull up, tristate, disable
   - slew-rate: 0 == slow, 1 == fast; generic pinconf does not display
 argument
 
 Great progress!!

Thans.

 
 (...)
  +++ b/arch/arm/mach-zynq/Kconfig
  @@ -9,6 +9,7 @@ config ARCH_ZYNQ
  select HAVE_ARM_TWD if SMP
  select ICST
  select MFD_SYSCON
  +   select PINCTRL
 
 Don't you also want to select PINCTRL_ZYNQ or is it
 really optional?

Yep, you're right. I did some testing and it is required. I already have
that included in my work tree.

 
  select SOC_BUS
  help
Support for Xilinx Zynq ARM Cortex A9 Platform
 
 Please split these machine changes into a separate patch. It is hitting
 a totally different subsystem.

OK

 
 (...)
  +++ b/drivers/pinctrl/pinctrl-zynq.c
 (...)
  +static const struct pinctrl_ops zynq_pctrl_ops = {
  +   .get_groups_count = zynq_pctrl_get_groups_count,
  +   .get_group_name = zynq_pctrl_get_group_name,
  +   .get_group_pins = zynq_pctrl_get_group_pins,
  +   .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
  +   .dt_free_map = pinctrl_utils_dt_free_map
  +};
 
 Nice use of generic functions!

Yeah, but for it to really work I need the changes I made to
pinconf-generic. Otherwise things just don't work well since I would
only be able to either select pin groups or pins in DT.

 
  +static int zynq_pinconf_cfg_get(struct pinctrl_dev *pctldev,
  +   unsigned pin,
  +   unsigned long *config)
  +{
  +   u32 reg;
  +   int ret;
  +   unsigned int arg = 0;
  +   unsigned int param = pinconf_to_config_param(*config);
  +   struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
  +
  +   if (pin  53)
  +   return -ENOTSUPP;
 
 53 looks a bit magical? #define or comment here to explain what's
 going on?

Yep, I'll add something like ZYNQ_NUM_MIOS

 
 Apart from these small things this looks like merge material.

That is good to hear, thank you. But before merging this the
pinconf-generic changes need to go through. Even though I didn't order
things that way in this series (I wanted to show how my work proceeded),
proper operation depends of the driver depends on those pinconf-generic
changes.

Thanks,
Sören
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Re: [PATCH RFC v2 1/8] pinctrl: Add driver for Zynq

2014-10-28 Thread Sören Brinkmann 
On Tue, 2014-10-28 at 04:16PM +0100, Lothar Waßmann wrote:
 Hi,
 
 Soren Brinkmann wrote:
  Signed-off-by: Soren Brinkmann soren.brinkm...@xilinx.com
  ---
  changes since RFC:
   - use syscon/regmap to access registers in SLCR space
   - add pinctrl to zc702 DT
   - rebase to 3.18: rename enable - set_mux
   - add kernel-doc
   - support pinconf
 - supported attributes
   - pin-bias: pull up, tristate, disable
   - slew-rate: 0 == slow, 1 == fast; generic pinconf does not display
 argument
  
 [...]
  +struct zynq_pctrl_group zynq_pctrl_groups[] = {
  +   DEFINE_ZYNQ_PINCTRL_GRP(ethernet0_0),
  +   DEFINE_ZYNQ_PINCTRL_GRP(ethernet1_0),
  +   DEFINE_ZYNQ_PINCTRL_GRP(mdio0_0),
  +   DEFINE_ZYNQ_PINCTRL_GRP(mdio1_0),
  +   DEFINE_ZYNQ_PINCTRL_GRP(qspi0_0),
  +   DEFINE_ZYNQ_PINCTRL_GRP(qspi1_0),
  +   DEFINE_ZYNQ_PINCTRL_GRP(qspi_fbclk),
  +   DEFINE_ZYNQ_PINCTRL_GRP(qspi_cs1),
  +   DEFINE_ZYNQ_PINCTRL_GRP(spi0_0),
  +   DEFINE_ZYNQ_PINCTRL_GRP(spi0_1),
  +   DEFINE_ZYNQ_PINCTRL_GRP(spi0_2),
  +   DEFINE_ZYNQ_PINCTRL_GRP(spi1_0),
  +   DEFINE_ZYNQ_PINCTRL_GRP(spi1_1),
  +   DEFINE_ZYNQ_PINCTRL_GRP(spi1_2),
  +   DEFINE_ZYNQ_PINCTRL_GRP(spi1_3),
  +   DEFINE_ZYNQ_PINCTRL_GRP(sdio0_0),
  +   DEFINE_ZYNQ_PINCTRL_GRP(sdio0_1),
  +   DEFINE_ZYNQ_PINCTRL_GRP(sdio0_2),
  +   DEFINE_ZYNQ_PINCTRL_GRP(sdio1_0),
  +   DEFINE_ZYNQ_PINCTRL_GRP(sdio1_1),
  +   DEFINE_ZYNQ_PINCTRL_GRP(sdio1_2),
  +   DEFINE_ZYNQ_PINCTRL_GRP(sdio1_3),
  +   DEFINE_ZYNQ_PINCTRL_GRP(sdio0_emio_wp),
  +   DEFINE_ZYNQ_PINCTRL_GRP(sdio0_emio_cd),
  +   DEFINE_ZYNQ_PINCTRL_GRP(sdio1_emio_wp),
  +   DEFINE_ZYNQ_PINCTRL_GRP(sdio1_emio_cd),
  +   DEFINE_ZYNQ_PINCTRL_GRP(smc0_nor),
  +   DEFINE_ZYNQ_PINCTRL_GRP(smc0_nor_cs1),
  +   DEFINE_ZYNQ_PINCTRL_GRP(smc0_nor_addr25),
  +   DEFINE_ZYNQ_PINCTRL_GRP(smc0_nand),
  +   DEFINE_ZYNQ_PINCTRL_GRP(can0_0),
  +   DEFINE_ZYNQ_PINCTRL_GRP(can0_1),
  +   DEFINE_ZYNQ_PINCTRL_GRP(can0_2),
  +   DEFINE_ZYNQ_PINCTRL_GRP(can0_3),
  +   DEFINE_ZYNQ_PINCTRL_GRP(can0_4),
  +   DEFINE_ZYNQ_PINCTRL_GRP(can0_5),
  +   DEFINE_ZYNQ_PINCTRL_GRP(can0_6),
  +   DEFINE_ZYNQ_PINCTRL_GRP(can0_7),
  +   DEFINE_ZYNQ_PINCTRL_GRP(can0_8),
  +   DEFINE_ZYNQ_PINCTRL_GRP(can0_9),
  +   DEFINE_ZYNQ_PINCTRL_GRP(can0_10),
  +   DEFINE_ZYNQ_PINCTRL_GRP(can1_0),
  +   DEFINE_ZYNQ_PINCTRL_GRP(can1_1),
  +   DEFINE_ZYNQ_PINCTRL_GRP(can1_2),
  +   DEFINE_ZYNQ_PINCTRL_GRP(can1_3),
  +   DEFINE_ZYNQ_PINCTRL_GRP(can1_4),
  +   DEFINE_ZYNQ_PINCTRL_GRP(can1_5),
  +   DEFINE_ZYNQ_PINCTRL_GRP(can1_6),
  +   DEFINE_ZYNQ_PINCTRL_GRP(can1_7),
  +   DEFINE_ZYNQ_PINCTRL_GRP(can1_8),
  +   DEFINE_ZYNQ_PINCTRL_GRP(can1_9),
  +   DEFINE_ZYNQ_PINCTRL_GRP(can1_10),
  +   DEFINE_ZYNQ_PINCTRL_GRP(can1_11),
  +   DEFINE_ZYNQ_PINCTRL_GRP(uart0_0),
  +   DEFINE_ZYNQ_PINCTRL_GRP(uart0_1),
  +   DEFINE_ZYNQ_PINCTRL_GRP(uart0_2),
  +   DEFINE_ZYNQ_PINCTRL_GRP(uart0_3),
  +   DEFINE_ZYNQ_PINCTRL_GRP(uart0_4),
  +   DEFINE_ZYNQ_PINCTRL_GRP(uart0_5),
  +   DEFINE_ZYNQ_PINCTRL_GRP(uart0_6),
  +   DEFINE_ZYNQ_PINCTRL_GRP(uart0_7),
  +   DEFINE_ZYNQ_PINCTRL_GRP(uart0_8),
  +   DEFINE_ZYNQ_PINCTRL_GRP(uart0_9),
  +   DEFINE_ZYNQ_PINCTRL_GRP(uart0_10),
  +   DEFINE_ZYNQ_PINCTRL_GRP(uart1_0),
  +   DEFINE_ZYNQ_PINCTRL_GRP(uart1_1),
  +   DEFINE_ZYNQ_PINCTRL_GRP(uart1_2),
  +   DEFINE_ZYNQ_PINCTRL_GRP(uart1_3),
  +   DEFINE_ZYNQ_PINCTRL_GRP(uart1_4),
  +   DEFINE_ZYNQ_PINCTRL_GRP(uart1_5),
  +   DEFINE_ZYNQ_PINCTRL_GRP(uart1_6),
  +   DEFINE_ZYNQ_PINCTRL_GRP(uart1_7),
  +   DEFINE_ZYNQ_PINCTRL_GRP(uart1_8),
  +   DEFINE_ZYNQ_PINCTRL_GRP(uart1_9),
  +   DEFINE_ZYNQ_PINCTRL_GRP(uart1_10),
  +   DEFINE_ZYNQ_PINCTRL_GRP(uart1_11),
  +   DEFINE_ZYNQ_PINCTRL_GRP(i2c0_0),
  +   DEFINE_ZYNQ_PINCTRL_GRP(i2c0_1),
  +   DEFINE_ZYNQ_PINCTRL_GRP(i2c0_2),
  +   DEFINE_ZYNQ_PINCTRL_GRP(i2c0_3),
  +   DEFINE_ZYNQ_PINCTRL_GRP(i2c0_4),
  +   DEFINE_ZYNQ_PINCTRL_GRP(i2c0_5),
  +   DEFINE_ZYNQ_PINCTRL_GRP(i2c0_6),
  +   DEFINE_ZYNQ_PINCTRL_GRP(i2c0_7),
  +   DEFINE_ZYNQ_PINCTRL_GRP(i2c0_8),
  +   DEFINE_ZYNQ_PINCTRL_GRP(i2c0_9),
  +   DEFINE_ZYNQ_PINCTRL_GRP(i2c0_10),
  +   DEFINE_ZYNQ_PINCTRL_GRP(i2c1_0),
  +   DEFINE_ZYNQ_PINCTRL_GRP(i2c1_1),
  +   DEFINE_ZYNQ_PINCTRL_GRP(i2c1_2),
  +   DEFINE_ZYNQ_PINCTRL_GRP(i2c1_3),
  +   DEFINE_ZYNQ_PINCTRL_GRP(i2c1_4),
  +   DEFINE_ZYNQ_PINCTRL_GRP(i2c1_5),
  +   DEFINE_ZYNQ_PINCTRL_GRP(i2c1_6),
  +   DEFINE_ZYNQ_PINCTRL_GRP(i2c1_7),
  +   DEFINE_ZYNQ_PINCTRL_GRP(i2c1_8),
  +   DEFINE_ZYNQ_PINCTRL_GRP(i2c1_9),
  +   DEFINE_ZYNQ_PINCTRL_GRP(i2c1_10),
  +   DEFINE_ZYNQ_PINCTRL_GRP(ttc0_0),
  +   DEFINE_ZYNQ_PINCTRL_GRP(ttc0_1),
  +   DEFINE_ZYNQ_PINCTRL_GRP(ttc0_2),
  +   DEFINE_ZYNQ_PINCTRL_GRP(ttc1_0),
  +   DEFINE_ZYNQ_PINCTRL_GRP(ttc1_1),
  +   DEFINE_ZYNQ_PINCTRL_GRP(ttc1_2),
  +   DEFINE_ZYNQ_PINCTRL_GRP(swdt0_0),
  +   DEFINE_ZYNQ_PINCTRL_GRP(swdt0_1),
  +   DEFINE_ZYNQ_PINCTRL_GRP(swdt0_2),
  +   DEFINE_ZYNQ_PINCTRL_GRP(swdt0_3),
  +   DEFINE_ZYNQ_PINCTRL_GRP(swdt0_4),
  +   DEFINE_ZYNQ_PINCTRL_GRP(gpio0_0),
  +

Re: [PATCH RFC v2 1/8] pinctrl: Add driver for Zynq

2014-10-28 Thread Lothar Waßmann 
Hi,

Sören Brinkmann wrote:
 On Tue, 2014-10-28 at 04:16PM +0100, Lothar Waßmann wrote:
  Hi,
  
  Soren Brinkmann wrote:
   Signed-off-by: Soren Brinkmann soren.brinkm...@xilinx.com
   ---
   changes since RFC:
- use syscon/regmap to access registers in SLCR space
- add pinctrl to zc702 DT
- rebase to 3.18: rename enable - set_mux
- add kernel-doc
- support pinconf
  - supported attributes
- pin-bias: pull up, tristate, disable
- slew-rate: 0 == slow, 1 == fast; generic pinconf does not display
  argument
   
  [...]
   +struct zynq_pctrl_group zynq_pctrl_groups[] = {
   + DEFINE_ZYNQ_PINCTRL_GRP(ethernet0_0),
   + DEFINE_ZYNQ_PINCTRL_GRP(ethernet1_0),
   + DEFINE_ZYNQ_PINCTRL_GRP(mdio0_0),
   + DEFINE_ZYNQ_PINCTRL_GRP(mdio1_0),
   + DEFINE_ZYNQ_PINCTRL_GRP(qspi0_0),
   + DEFINE_ZYNQ_PINCTRL_GRP(qspi1_0),
   + DEFINE_ZYNQ_PINCTRL_GRP(qspi_fbclk),
   + DEFINE_ZYNQ_PINCTRL_GRP(qspi_cs1),
   + DEFINE_ZYNQ_PINCTRL_GRP(spi0_0),
   + DEFINE_ZYNQ_PINCTRL_GRP(spi0_1),
   + DEFINE_ZYNQ_PINCTRL_GRP(spi0_2),
   + DEFINE_ZYNQ_PINCTRL_GRP(spi1_0),
   + DEFINE_ZYNQ_PINCTRL_GRP(spi1_1),
   + DEFINE_ZYNQ_PINCTRL_GRP(spi1_2),
   + DEFINE_ZYNQ_PINCTRL_GRP(spi1_3),
   + DEFINE_ZYNQ_PINCTRL_GRP(sdio0_0),
   + DEFINE_ZYNQ_PINCTRL_GRP(sdio0_1),
   + DEFINE_ZYNQ_PINCTRL_GRP(sdio0_2),
   + DEFINE_ZYNQ_PINCTRL_GRP(sdio1_0),
   + DEFINE_ZYNQ_PINCTRL_GRP(sdio1_1),
   + DEFINE_ZYNQ_PINCTRL_GRP(sdio1_2),
   + DEFINE_ZYNQ_PINCTRL_GRP(sdio1_3),
   + DEFINE_ZYNQ_PINCTRL_GRP(sdio0_emio_wp),
   + DEFINE_ZYNQ_PINCTRL_GRP(sdio0_emio_cd),
   + DEFINE_ZYNQ_PINCTRL_GRP(sdio1_emio_wp),
   + DEFINE_ZYNQ_PINCTRL_GRP(sdio1_emio_cd),
   + DEFINE_ZYNQ_PINCTRL_GRP(smc0_nor),
   + DEFINE_ZYNQ_PINCTRL_GRP(smc0_nor_cs1),
   + DEFINE_ZYNQ_PINCTRL_GRP(smc0_nor_addr25),
   + DEFINE_ZYNQ_PINCTRL_GRP(smc0_nand),
   + DEFINE_ZYNQ_PINCTRL_GRP(can0_0),
   + DEFINE_ZYNQ_PINCTRL_GRP(can0_1),
   + DEFINE_ZYNQ_PINCTRL_GRP(can0_2),
   + DEFINE_ZYNQ_PINCTRL_GRP(can0_3),
   + DEFINE_ZYNQ_PINCTRL_GRP(can0_4),
   + DEFINE_ZYNQ_PINCTRL_GRP(can0_5),
   + DEFINE_ZYNQ_PINCTRL_GRP(can0_6),
   + DEFINE_ZYNQ_PINCTRL_GRP(can0_7),
   + DEFINE_ZYNQ_PINCTRL_GRP(can0_8),
   + DEFINE_ZYNQ_PINCTRL_GRP(can0_9),
   + DEFINE_ZYNQ_PINCTRL_GRP(can0_10),
   + DEFINE_ZYNQ_PINCTRL_GRP(can1_0),
   + DEFINE_ZYNQ_PINCTRL_GRP(can1_1),
   + DEFINE_ZYNQ_PINCTRL_GRP(can1_2),
   + DEFINE_ZYNQ_PINCTRL_GRP(can1_3),
   + DEFINE_ZYNQ_PINCTRL_GRP(can1_4),
   + DEFINE_ZYNQ_PINCTRL_GRP(can1_5),
   + DEFINE_ZYNQ_PINCTRL_GRP(can1_6),
   + DEFINE_ZYNQ_PINCTRL_GRP(can1_7),
   + DEFINE_ZYNQ_PINCTRL_GRP(can1_8),
   + DEFINE_ZYNQ_PINCTRL_GRP(can1_9),
   + DEFINE_ZYNQ_PINCTRL_GRP(can1_10),
   + DEFINE_ZYNQ_PINCTRL_GRP(can1_11),
   + DEFINE_ZYNQ_PINCTRL_GRP(uart0_0),
   + DEFINE_ZYNQ_PINCTRL_GRP(uart0_1),
   + DEFINE_ZYNQ_PINCTRL_GRP(uart0_2),
   + DEFINE_ZYNQ_PINCTRL_GRP(uart0_3),
   + DEFINE_ZYNQ_PINCTRL_GRP(uart0_4),
   + DEFINE_ZYNQ_PINCTRL_GRP(uart0_5),
   + DEFINE_ZYNQ_PINCTRL_GRP(uart0_6),
   + DEFINE_ZYNQ_PINCTRL_GRP(uart0_7),
   + DEFINE_ZYNQ_PINCTRL_GRP(uart0_8),
   + DEFINE_ZYNQ_PINCTRL_GRP(uart0_9),
   + DEFINE_ZYNQ_PINCTRL_GRP(uart0_10),
   + DEFINE_ZYNQ_PINCTRL_GRP(uart1_0),
   + DEFINE_ZYNQ_PINCTRL_GRP(uart1_1),
   + DEFINE_ZYNQ_PINCTRL_GRP(uart1_2),
   + DEFINE_ZYNQ_PINCTRL_GRP(uart1_3),
   + DEFINE_ZYNQ_PINCTRL_GRP(uart1_4),
   + DEFINE_ZYNQ_PINCTRL_GRP(uart1_5),
   + DEFINE_ZYNQ_PINCTRL_GRP(uart1_6),
   + DEFINE_ZYNQ_PINCTRL_GRP(uart1_7),
   + DEFINE_ZYNQ_PINCTRL_GRP(uart1_8),
   + DEFINE_ZYNQ_PINCTRL_GRP(uart1_9),
   + DEFINE_ZYNQ_PINCTRL_GRP(uart1_10),
   + DEFINE_ZYNQ_PINCTRL_GRP(uart1_11),
   + DEFINE_ZYNQ_PINCTRL_GRP(i2c0_0),
   + DEFINE_ZYNQ_PINCTRL_GRP(i2c0_1),
   + DEFINE_ZYNQ_PINCTRL_GRP(i2c0_2),
   + DEFINE_ZYNQ_PINCTRL_GRP(i2c0_3),
   + DEFINE_ZYNQ_PINCTRL_GRP(i2c0_4),
   + DEFINE_ZYNQ_PINCTRL_GRP(i2c0_5),
   + DEFINE_ZYNQ_PINCTRL_GRP(i2c0_6),
   + DEFINE_ZYNQ_PINCTRL_GRP(i2c0_7),
   + DEFINE_ZYNQ_PINCTRL_GRP(i2c0_8),
   + DEFINE_ZYNQ_PINCTRL_GRP(i2c0_9),
   + DEFINE_ZYNQ_PINCTRL_GRP(i2c0_10),
   + DEFINE_ZYNQ_PINCTRL_GRP(i2c1_0),
   + DEFINE_ZYNQ_PINCTRL_GRP(i2c1_1),
   + DEFINE_ZYNQ_PINCTRL_GRP(i2c1_2),
   + DEFINE_ZYNQ_PINCTRL_GRP(i2c1_3),
   + DEFINE_ZYNQ_PINCTRL_GRP(i2c1_4),
   + DEFINE_ZYNQ_PINCTRL_GRP(i2c1_5),
   + DEFINE_ZYNQ_PINCTRL_GRP(i2c1_6),
   + DEFINE_ZYNQ_PINCTRL_GRP(i2c1_7),
   + DEFINE_ZYNQ_PINCTRL_GRP(i2c1_8),
   + DEFINE_ZYNQ_PINCTRL_GRP(i2c1_9),
   + DEFINE_ZYNQ_PINCTRL_GRP(i2c1_10),
   + DEFINE_ZYNQ_PINCTRL_GRP(ttc0_0),
   + DEFINE_ZYNQ_PINCTRL_GRP(ttc0_1),
   + DEFINE_ZYNQ_PINCTRL_GRP(ttc0_2),
   + DEFINE_ZYNQ_PINCTRL_GRP(ttc1_0),
   + DEFINE_ZYNQ_PINCTRL_GRP(ttc1_1),
   + DEFINE_ZYNQ_PINCTRL_GRP(ttc1_2),
   + DEFINE_ZYNQ_PINCTRL_GRP(swdt0_0),
   + DEFINE_ZYNQ_PINCTRL_GRP(swdt0_1),
   + DEFINE_ZYNQ_PINCTRL_GRP(swdt0_2),
   + DEFINE_ZYNQ_PINCTRL_GRP(swdt0_3),
   + DEFINE_ZYNQ_PINCTRL_GRP(swdt0_4),
   + DEFINE_ZYNQ_PINCTRL_GRP(gpio0_0),
   + DEFINE_ZYNQ_PINCTRL_GRP(gpio0_1),
   + DEFINE_ZYNQ_PINCTRL_GRP(gpio0_2),
   +

[PATCH RFC v2 1/8] pinctrl: Add driver for Zynq

2014-10-16 Thread Soren Brinkmann 
Signed-off-by: Soren Brinkmann 
---
changes since RFC:
 - use syscon/regmap to access registers in SLCR space
 - add pinctrl to zc702 DT
 - rebase to 3.18: rename enable -> set_mux
 - add kernel-doc
 - support pinconf
   - supported attributes
 - pin-bias: pull up, tristate, disable
 - slew-rate: 0 == slow, 1 == fast; generic pinconf does not display
   argument

---
 arch/arm/mach-zynq/Kconfig |1 +
 drivers/pinctrl/Kconfig|8 +
 drivers/pinctrl/Makefile   |1 +
 drivers/pinctrl/pinctrl-zynq.c | 1091 
 4 files changed, 1101 insertions(+)
 create mode 100644 drivers/pinctrl/pinctrl-zynq.c

diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig
index aaa5162c1509..13b8524354ee 100644
--- a/arch/arm/mach-zynq/Kconfig
+++ b/arch/arm/mach-zynq/Kconfig
@@ -9,6 +9,7 @@ config ARCH_ZYNQ
select HAVE_ARM_TWD if SMP
select ICST
select MFD_SYSCON
+   select PINCTRL
select SOC_BUS
help
  Support for Xilinx Zynq ARM Cortex A9 Platform
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index c6a66de6ed72..33cbae0a7f6f 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -203,6 +203,14 @@ config PINCTRL_PALMAS
  open drain configuration for the Palmas series devices like
  TPS65913, TPS80036 etc.
 
+config PINCTRL_ZYNQ
+   bool "Pinctrl driver for Xilinx Zynq"
+   depends on ARCH_ZYNQ
+   select PINMUX
+   select GENERIC_PINCONF
+   help
+ This selectes the pinctrl driver for Xilinx Zynq.
+
 source "drivers/pinctrl/berlin/Kconfig"
 source "drivers/pinctrl/freescale/Kconfig"
 source "drivers/pinctrl/mvebu/Kconfig"
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 51f52d32859e..aa999cf57f04 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -36,6 +36,7 @@ obj-$(CONFIG_PINCTRL_XWAY)+= pinctrl-xway.o
 obj-$(CONFIG_PINCTRL_LANTIQ)   += pinctrl-lantiq.o
 obj-$(CONFIG_PINCTRL_TB10X)+= pinctrl-tb10x.o
 obj-$(CONFIG_PINCTRL_ST)   += pinctrl-st.o
+obj-$(CONFIG_PINCTRL_ZYNQ) += pinctrl-zynq.o
 
 obj-$(CONFIG_ARCH_BERLIN)  += berlin/
 obj-y  += freescale/
diff --git a/drivers/pinctrl/pinctrl-zynq.c b/drivers/pinctrl/pinctrl-zynq.c
new file mode 100644
index ..a32fac61cba0
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-zynq.c
@@ -0,0 +1,1091 @@
+/*
+ * Zynq pin controller
+ *
+ *  Copyright (C) 2014 Xilinx
+ *
+ *  Sören Brinkmann 
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see .
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "pinctrl-utils.h"
+#include "core.h"
+
+#define ZYNQ_PCTRL_MIO_MST_TRI00x10c
+#define ZYNQ_PCTRL_MIO_MST_TRI10x110
+
+#define ZYNQ_PINMUX_MUX_SHIFT  1
+#define ZYNQ_PINMUX_MUX_MASK   (0x7f << ZYNQ_PINMUX_MUX_SHIFT)
+
+/**
+ * struct zynq_pinctrl - driver data
+ * @pctrl: Pinctrl device
+ * @syscon:Syscon regmap
+ * @pctrl_offset:  Offset for pinctrl into the @syscon space
+ * @groups:Pingroups
+ * @ngroupos:  Number of @groups
+ * @funcs: Pinmux functions
+ * @nfuncs:Number of @funcs
+ */
+struct zynq_pinctrl {
+   struct pinctrl_dev *pctrl;
+   struct regmap *syscon;
+   u32 pctrl_offset;
+   const struct zynq_pctrl_group *groups;
+   unsigned int ngroups;
+   const struct zynq_pinmux_function *funcs;
+   unsigned int nfuncs;
+};
+
+struct zynq_pctrl_group {
+   const char *name;
+   const unsigned int *pins;
+   const unsigned npins;
+};
+
+/**
+ * struct zynq_pinmux_function - a pinmux function
+ * @name:  Name of the pinmux function.
+ * @groups:List of pingroups for this function.
+ * @ngroups:   Number of entries in @groups.
+ * @mux_val:   Selector for this function
+ * @mux:   Offset of function specific mux
+ * @mux_mask:  Mask for function specific selector
+ * @mux_shift: Shift for function specific selector
+ */
+struct zynq_pinmux_function {
+   const char *name;
+   const char * const *groups;
+   unsigned int ngroups;
+   unsigned int mux_val;
+   u32 mux;
+   u32 mux_mask;
+   u8 mux_shift;
+};
+
+enum zynq_pinmux_functions {
+

[PATCH RFC v2 1/8] pinctrl: Add driver for Zynq

2014-10-16 Thread Soren Brinkmann 
Signed-off-by: Soren Brinkmann soren.brinkm...@xilinx.com
---
changes since RFC:
 - use syscon/regmap to access registers in SLCR space
 - add pinctrl to zc702 DT
 - rebase to 3.18: rename enable - set_mux
 - add kernel-doc
 - support pinconf
   - supported attributes
 - pin-bias: pull up, tristate, disable
 - slew-rate: 0 == slow, 1 == fast; generic pinconf does not display
   argument

---
 arch/arm/mach-zynq/Kconfig |1 +
 drivers/pinctrl/Kconfig|8 +
 drivers/pinctrl/Makefile   |1 +
 drivers/pinctrl/pinctrl-zynq.c | 1091 
 4 files changed, 1101 insertions(+)
 create mode 100644 drivers/pinctrl/pinctrl-zynq.c

diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig
index aaa5162c1509..13b8524354ee 100644
--- a/arch/arm/mach-zynq/Kconfig
+++ b/arch/arm/mach-zynq/Kconfig
@@ -9,6 +9,7 @@ config ARCH_ZYNQ
select HAVE_ARM_TWD if SMP
select ICST
select MFD_SYSCON
+   select PINCTRL
select SOC_BUS
help
  Support for Xilinx Zynq ARM Cortex A9 Platform
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index c6a66de6ed72..33cbae0a7f6f 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -203,6 +203,14 @@ config PINCTRL_PALMAS
  open drain configuration for the Palmas series devices like
  TPS65913, TPS80036 etc.
 
+config PINCTRL_ZYNQ
+   bool Pinctrl driver for Xilinx Zynq
+   depends on ARCH_ZYNQ
+   select PINMUX
+   select GENERIC_PINCONF
+   help
+ This selectes the pinctrl driver for Xilinx Zynq.
+
 source drivers/pinctrl/berlin/Kconfig
 source drivers/pinctrl/freescale/Kconfig
 source drivers/pinctrl/mvebu/Kconfig
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 51f52d32859e..aa999cf57f04 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -36,6 +36,7 @@ obj-$(CONFIG_PINCTRL_XWAY)+= pinctrl-xway.o
 obj-$(CONFIG_PINCTRL_LANTIQ)   += pinctrl-lantiq.o
 obj-$(CONFIG_PINCTRL_TB10X)+= pinctrl-tb10x.o
 obj-$(CONFIG_PINCTRL_ST)   += pinctrl-st.o
+obj-$(CONFIG_PINCTRL_ZYNQ) += pinctrl-zynq.o
 
 obj-$(CONFIG_ARCH_BERLIN)  += berlin/
 obj-y  += freescale/
diff --git a/drivers/pinctrl/pinctrl-zynq.c b/drivers/pinctrl/pinctrl-zynq.c
new file mode 100644
index ..a32fac61cba0
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-zynq.c
@@ -0,0 +1,1091 @@
+/*
+ * Zynq pin controller
+ *
+ *  Copyright (C) 2014 Xilinx
+ *
+ *  Sören Brinkmann soren.brinkm...@xilinx.com
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see http://www.gnu.org/licenses/.
+ */
+#include linux/io.h
+#include linux/mfd/syscon.h
+#include linux/module.h
+#include linux/of.h
+#include linux/platform_device.h
+#include linux/pinctrl/pinctrl.h
+#include linux/pinctrl/pinmux.h
+#include linux/pinctrl/pinconf.h
+#include linux/pinctrl/pinconf-generic.h
+#include linux/regmap.h
+#include pinctrl-utils.h
+#include core.h
+
+#define ZYNQ_PCTRL_MIO_MST_TRI00x10c
+#define ZYNQ_PCTRL_MIO_MST_TRI10x110
+
+#define ZYNQ_PINMUX_MUX_SHIFT  1
+#define ZYNQ_PINMUX_MUX_MASK   (0x7f  ZYNQ_PINMUX_MUX_SHIFT)
+
+/**
+ * struct zynq_pinctrl - driver data
+ * @pctrl: Pinctrl device
+ * @syscon:Syscon regmap
+ * @pctrl_offset:  Offset for pinctrl into the @syscon space
+ * @groups:Pingroups
+ * @ngroupos:  Number of @groups
+ * @funcs: Pinmux functions
+ * @nfuncs:Number of @funcs
+ */
+struct zynq_pinctrl {
+   struct pinctrl_dev *pctrl;
+   struct regmap *syscon;
+   u32 pctrl_offset;
+   const struct zynq_pctrl_group *groups;
+   unsigned int ngroups;
+   const struct zynq_pinmux_function *funcs;
+   unsigned int nfuncs;
+};
+
+struct zynq_pctrl_group {
+   const char *name;
+   const unsigned int *pins;
+   const unsigned npins;
+};
+
+/**
+ * struct zynq_pinmux_function - a pinmux function
+ * @name:  Name of the pinmux function.
+ * @groups:List of pingroups for this function.
+ * @ngroups:   Number of entries in @groups.
+ * @mux_val:   Selector for this function
+ * @mux:   Offset of function specific mux
+ * @mux_mask:  Mask for function specific selector
+ * @mux_shift: Shift for function specific selector
+ */
+struct zynq_pinmux_function {
+   const char