Re: [PATCH V1 24/26] spi: tegra114: de-assert CS before SPI mode is reset to its default

On Mon, Apr 01, 2019 at 06:07:45PM +, Sowjanya Komatineni wrote: > I see you have applied some patches in V1 series so should I re-send > again those as well along with feedback changes in next version or > just only the patches that are not applied. Please don't resend already applied

RE: [PATCH V1 24/26] spi: tegra114: de-assert CS before SPI mode is reset to its default

> On Tue, Mar 26, 2019 at 10:56:45PM -0700, Sowjanya Komatineni wrote: > > With SW CS, during transfer completion CS is de-asserted by writing > > the default command1 register value to SPI_COMMAND1 register. With > > this both mode and CS state are set at the same time and if current > >

Re: [PATCH V1 24/26] spi: tegra114: de-assert CS before SPI mode is reset to its default

On Tue, Mar 26, 2019 at 10:56:45PM -0700, Sowjanya Komatineni wrote: > With SW CS, during transfer completion CS is de-asserted by writing the > default command1 register value to SPI_COMMAND1 register. With this both > mode and CS state are set at the same time and if current transfer mode > is

[PATCH V1 24/26] spi: tegra114: de-assert CS before SPI mode is reset to its default

With SW CS, during transfer completion CS is de-asserted by writing the default command1 register value to SPI_COMMAND1 register. With this both mode and CS state are set at the same time and if current transfer mode is different to default SPI mode and if mode change happens prior to CS