Re: [PATCH V2] iommu/amd - Set the device table entry PPR bit for IOMMU V2 devices

2017-12-20 Thread Gary R Hook
On 12/20/2017 01:02 PM, Alex Williamson wrote: On Tue, 19 Dec 2017 16:15:41 -0600 Gary R Hook wrote: The AMD IOMMU specification Rev 3.00 (December 2016) introduces a new Enhanced PPR Handling Support (EPHSup) bit in the MMIO register offset 0030h (IOMMU Extended Feature

Re: [PATCH V2] iommu/amd - Set the device table entry PPR bit for IOMMU V2 devices

2017-12-20 Thread Gary R Hook
On 12/20/2017 01:02 PM, Alex Williamson wrote: On Tue, 19 Dec 2017 16:15:41 -0600 Gary R Hook wrote: The AMD IOMMU specification Rev 3.00 (December 2016) introduces a new Enhanced PPR Handling Support (EPHSup) bit in the MMIO register offset 0030h (IOMMU Extended Feature Register). When

Re: [PATCH V2] iommu/amd - Set the device table entry PPR bit for IOMMU V2 devices

2017-12-20 Thread Alex Williamson
On Tue, 19 Dec 2017 16:15:41 -0600 Gary R Hook wrote: > The AMD IOMMU specification Rev 3.00 (December 2016) introduces a > new Enhanced PPR Handling Support (EPHSup) bit in the MMIO register > offset 0030h (IOMMU Extended Feature Register). > > When EPHSup=1, the IOMMU

Re: [PATCH V2] iommu/amd - Set the device table entry PPR bit for IOMMU V2 devices

2017-12-20 Thread Alex Williamson
On Tue, 19 Dec 2017 16:15:41 -0600 Gary R Hook wrote: > The AMD IOMMU specification Rev 3.00 (December 2016) introduces a > new Enhanced PPR Handling Support (EPHSup) bit in the MMIO register > offset 0030h (IOMMU Extended Feature Register). > > When EPHSup=1, the IOMMU hardware requires the

[PATCH V2] iommu/amd - Set the device table entry PPR bit for IOMMU V2 devices

2017-12-19 Thread Gary R Hook
The AMD IOMMU specification Rev 3.00 (December 2016) introduces a new Enhanced PPR Handling Support (EPHSup) bit in the MMIO register offset 0030h (IOMMU Extended Feature Register). When EPHSup=1, the IOMMU hardware requires the PPR bit of the device table entry (DTE) to be set in order to

[PATCH V2] iommu/amd - Set the device table entry PPR bit for IOMMU V2 devices

2017-12-19 Thread Gary R Hook
The AMD IOMMU specification Rev 3.00 (December 2016) introduces a new Enhanced PPR Handling Support (EPHSup) bit in the MMIO register offset 0030h (IOMMU Extended Feature Register). When EPHSup=1, the IOMMU hardware requires the PPR bit of the device table entry (DTE) to be set in order to