On Fri, Nov 14, 2014 at 7:04 AM, Mark Brown wrote:
> On Thu, Nov 13, 2014 at 05:36:31PM +, Mark Brown wrote:
>> On Wed, Nov 12, 2014 at 07:08:14PM -0800, Andrew Bresticker wrote:
>> > This series adds support for the Sychronous Peripheral Flash Interface
>> > master found on IMG SoCs. The
On Thu, Nov 13, 2014 at 05:36:31PM +, Mark Brown wrote:
> On Wed, Nov 12, 2014 at 07:08:14PM -0800, Andrew Bresticker wrote:
> > This series adds support for the Sychronous Peripheral Flash Interface
> > master found on IMG SoCs. The controller supports up to 5 chip-select
> > lines and
On Thu, Nov 13, 2014 at 05:36:31PM +, Mark Brown wrote:
On Wed, Nov 12, 2014 at 07:08:14PM -0800, Andrew Bresticker wrote:
This series adds support for the Sychronous Peripheral Flash Interface
master found on IMG SoCs. The controller supports up to 5 chip-select
lines and single,
On Fri, Nov 14, 2014 at 7:04 AM, Mark Brown broo...@kernel.org wrote:
On Thu, Nov 13, 2014 at 05:36:31PM +, Mark Brown wrote:
On Wed, Nov 12, 2014 at 07:08:14PM -0800, Andrew Bresticker wrote:
This series adds support for the Sychronous Peripheral Flash Interface
master found on IMG
On Wed, Nov 12, 2014 at 07:08:14PM -0800, Andrew Bresticker wrote:
> This series adds support for the Sychronous Peripheral Flash Interface
> master found on IMG SoCs. The controller supports up to 5 chip-select
> lines and single, dual, and optionally quad, mode transfers.
Applied both, thanks.
On Wed, Nov 12, 2014 at 07:08:14PM -0800, Andrew Bresticker wrote:
This series adds support for the Sychronous Peripheral Flash Interface
master found on IMG SoCs. The controller supports up to 5 chip-select
lines and single, dual, and optionally quad, mode transfers.
Applied both, thanks.
This series adds support for the Sychronous Peripheral Flash Interface
master found on IMG SoCs. The controller supports up to 5 chip-select
lines and single, dual, and optionally quad, mode transfers.
Tested on a platform using the MIPS-based Pistachio SoC with additional
out-of-tree patches -
This series adds support for the Sychronous Peripheral Flash Interface
master found on IMG SoCs. The controller supports up to 5 chip-select
lines and single, dual, and optionally quad, mode transfers.
Tested on a platform using the MIPS-based Pistachio SoC with additional
out-of-tree patches -
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