Re: [PATCH V4 09/12] clk: sprd: Add dt-bindings include file for SC9860

2017-11-10 Thread Rob Herring 
On Fri, Nov 10, 2017 at 02:36:04PM +0800, Chunyan Zhang wrote:
> This file defines all SC9860 clock indexes, it should be included in the
> device tree in which there's device using the clocks.
> 
> Signed-off-by: Chunyan Zhang 
> ---
>  include/dt-bindings/clock/sprd,sc9860-clk.h | 408 
> 
>  1 file changed, 408 insertions(+)
>  create mode 100644 include/dt-bindings/clock/sprd,sc9860-clk.h

Acked-by: Rob Herring

Re: [PATCH V4 09/12] clk: sprd: Add dt-bindings include file for SC9860

2017-11-10 Thread Rob Herring 
On Fri, Nov 10, 2017 at 02:36:04PM +0800, Chunyan Zhang wrote:
> This file defines all SC9860 clock indexes, it should be included in the
> device tree in which there's device using the clocks.
> 
> Signed-off-by: Chunyan Zhang 
> ---
>  include/dt-bindings/clock/sprd,sc9860-clk.h | 408 
> 
>  1 file changed, 408 insertions(+)
>  create mode 100644 include/dt-bindings/clock/sprd,sc9860-clk.h

Acked-by: Rob Herring

[PATCH V4 09/12] clk: sprd: Add dt-bindings include file for SC9860

2017-11-09 Thread Chunyan Zhang 
This file defines all SC9860 clock indexes, it should be included in the
device tree in which there's device using the clocks.

Signed-off-by: Chunyan Zhang 
---
 include/dt-bindings/clock/sprd,sc9860-clk.h | 408 
 1 file changed, 408 insertions(+)
 create mode 100644 include/dt-bindings/clock/sprd,sc9860-clk.h

diff --git a/include/dt-bindings/clock/sprd,sc9860-clk.h 
b/include/dt-bindings/clock/sprd,sc9860-clk.h
new file mode 100644
index 000..48e6052
--- /dev/null
+++ b/include/dt-bindings/clock/sprd,sc9860-clk.h
@@ -0,0 +1,408 @@
+/*
+ * Spreadtrum SC9860 platform clocks
+ *
+ * Copyright (C) 2017, Spreadtrum Communications Inc.
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ */
+
+#ifndef _DT_BINDINGS_CLK_SC9860_H_
+#define _DT_BINDINGS_CLK_SC9860_H_
+
+#defineCLK_EXT_RCO_100M0
+#defineCLK_EXT_32K 1
+#defineCLK_FAC_4M  2
+#defineCLK_FAC_2M  3
+#defineCLK_FAC_1M  4
+#defineCLK_FAC_250K5
+#defineCLK_FAC_RPLL0_26M   6
+#defineCLK_FAC_RPLL1_26M   7
+#defineCLK_FAC_RCO25M  8
+#defineCLK_FAC_RCO4M   9
+#defineCLK_FAC_RCO2M   10
+#defineCLK_FAC_3K2 11
+#defineCLK_FAC_1K  12
+#defineCLK_MPLL0_GATE  13
+#defineCLK_MPLL1_GATE  14
+#defineCLK_DPLL0_GATE  15
+#defineCLK_DPLL1_GATE  16
+#defineCLK_LTEPLL0_GATE17
+#defineCLK_TWPLL_GATE  18
+#defineCLK_LTEPLL1_GATE19
+#defineCLK_RPLL0_GATE  20
+#defineCLK_RPLL1_GATE  21
+#defineCLK_CPPLL_GATE  22
+#defineCLK_GPLL_GATE   23
+#define CLK_PMU_GATE_NUM   (CLK_GPLL_GATE + 1)
+
+#defineCLK_MPLL0   0
+#defineCLK_MPLL1   1
+#defineCLK_DPLL0   2
+#defineCLK_DPLL1   3
+#defineCLK_RPLL0   4
+#defineCLK_RPLL1   5
+#defineCLK_TWPLL   6
+#defineCLK_LTEPLL0 7
+#defineCLK_LTEPLL1 8
+#defineCLK_GPLL9
+#defineCLK_CPPLL   10
+#defineCLK_GPLL_42M5   11
+#defineCLK_TWPLL_768M  12
+#defineCLK_TWPLL_384M  13
+#defineCLK_TWPLL_192M  14
+#defineCLK_TWPLL_96M   15
+#defineCLK_TWPLL_48M   16
+#defineCLK_TWPLL_24M   17
+#defineCLK_TWPLL_12M   18
+#defineCLK_TWPLL_512M  19
+#defineCLK_TWPLL_256M  20
+#defineCLK_TWPLL_128M  21
+#defineCLK_TWPLL_64M   22
+#defineCLK_TWPLL_307M2 23
+#defineCLK_TWPLL_153M6 24
+#defineCLK_TWPLL_76M8  25
+#defineCLK_TWPLL_51M2  26
+#defineCLK_TWPLL_38M4  27
+#defineCLK_TWPLL_19M2  28
+#defineCLK_L0_614M429
+#defineCLK_L0_409M630
+#defineCLK_L0_38M  31
+#defineCLK_L1_38M  32
+#defineCLK_RPLL0_192M  33
+#defineCLK_RPLL0_96M   34
+#defineCLK_RPLL0_48M   35
+#defineCLK_RPLL1_468M  36
+#defineCLK_RPLL1_192M  37
+#defineCLK_RPLL1_96M   38
+#defineCLK_RPLL1_64M   39
+#defineCLK_RPLL1_48M   40
+#defineCLK_DPLL0_50M   41
+#defineCLK_DPLL1_50M   42
+#defineCLK_CPPLL_50M   43
+#defineCLK_M0_39M  44
+#defineCLK_M1_63M  45
+#define CLK_PLL_NUM(CLK_M1_63M + 1)
+
+
+#defineCLK_AP_APB  0
+#defineCLK_AP_USB3 1
+#defineCLK_UART0   2
+#defineCLK_UART1   3
+#defineCLK_UART2   4
+#defineCLK_UART3   5
+#defineCLK_UART4   6
+#defineCLK_I2C07
+#defineCLK_I2C18
+#defineCLK_I2C29
+#defineCLK_I2C310
+#defineCLK_I2C411
+#defineCLK_I2C512
+#defineCLK_SPI013
+#defineCLK_SPI114
+#defineCLK_SPI215
+#defineCLK_SPI316
+#defineCLK_IIS017
+#defineCLK_IIS118
+#defineCLK_IIS219
+#defineCLK_IIS320
+#define CLK_AP_CLK_NUM (CLK_IIS3 + 1)
+
+#defineCLK_AON_APB 0
+#defineCLK_AUX01
+#defineCLK_AUX1

[PATCH V4 09/12] clk: sprd: Add dt-bindings include file for SC9860

2017-11-09 Thread Chunyan Zhang 
This file defines all SC9860 clock indexes, it should be included in the
device tree in which there's device using the clocks.

Signed-off-by: Chunyan Zhang 
---
 include/dt-bindings/clock/sprd,sc9860-clk.h | 408 
 1 file changed, 408 insertions(+)
 create mode 100644 include/dt-bindings/clock/sprd,sc9860-clk.h

diff --git a/include/dt-bindings/clock/sprd,sc9860-clk.h 
b/include/dt-bindings/clock/sprd,sc9860-clk.h
new file mode 100644
index 000..48e6052
--- /dev/null
+++ b/include/dt-bindings/clock/sprd,sc9860-clk.h
@@ -0,0 +1,408 @@
+/*
+ * Spreadtrum SC9860 platform clocks
+ *
+ * Copyright (C) 2017, Spreadtrum Communications Inc.
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ */
+
+#ifndef _DT_BINDINGS_CLK_SC9860_H_
+#define _DT_BINDINGS_CLK_SC9860_H_
+
+#defineCLK_EXT_RCO_100M0
+#defineCLK_EXT_32K 1
+#defineCLK_FAC_4M  2
+#defineCLK_FAC_2M  3
+#defineCLK_FAC_1M  4
+#defineCLK_FAC_250K5
+#defineCLK_FAC_RPLL0_26M   6
+#defineCLK_FAC_RPLL1_26M   7
+#defineCLK_FAC_RCO25M  8
+#defineCLK_FAC_RCO4M   9
+#defineCLK_FAC_RCO2M   10
+#defineCLK_FAC_3K2 11
+#defineCLK_FAC_1K  12
+#defineCLK_MPLL0_GATE  13
+#defineCLK_MPLL1_GATE  14
+#defineCLK_DPLL0_GATE  15
+#defineCLK_DPLL1_GATE  16
+#defineCLK_LTEPLL0_GATE17
+#defineCLK_TWPLL_GATE  18
+#defineCLK_LTEPLL1_GATE19
+#defineCLK_RPLL0_GATE  20
+#defineCLK_RPLL1_GATE  21
+#defineCLK_CPPLL_GATE  22
+#defineCLK_GPLL_GATE   23
+#define CLK_PMU_GATE_NUM   (CLK_GPLL_GATE + 1)
+
+#defineCLK_MPLL0   0
+#defineCLK_MPLL1   1
+#defineCLK_DPLL0   2
+#defineCLK_DPLL1   3
+#defineCLK_RPLL0   4
+#defineCLK_RPLL1   5
+#defineCLK_TWPLL   6
+#defineCLK_LTEPLL0 7
+#defineCLK_LTEPLL1 8
+#defineCLK_GPLL9
+#defineCLK_CPPLL   10
+#defineCLK_GPLL_42M5   11
+#defineCLK_TWPLL_768M  12
+#defineCLK_TWPLL_384M  13
+#defineCLK_TWPLL_192M  14
+#defineCLK_TWPLL_96M   15
+#defineCLK_TWPLL_48M   16
+#defineCLK_TWPLL_24M   17
+#defineCLK_TWPLL_12M   18
+#defineCLK_TWPLL_512M  19
+#defineCLK_TWPLL_256M  20
+#defineCLK_TWPLL_128M  21
+#defineCLK_TWPLL_64M   22
+#defineCLK_TWPLL_307M2 23
+#defineCLK_TWPLL_153M6 24
+#defineCLK_TWPLL_76M8  25
+#defineCLK_TWPLL_51M2  26
+#defineCLK_TWPLL_38M4  27
+#defineCLK_TWPLL_19M2  28
+#defineCLK_L0_614M429
+#defineCLK_L0_409M630
+#defineCLK_L0_38M  31
+#defineCLK_L1_38M  32
+#defineCLK_RPLL0_192M  33
+#defineCLK_RPLL0_96M   34
+#defineCLK_RPLL0_48M   35
+#defineCLK_RPLL1_468M  36
+#defineCLK_RPLL1_192M  37
+#defineCLK_RPLL1_96M   38
+#defineCLK_RPLL1_64M   39
+#defineCLK_RPLL1_48M   40
+#defineCLK_DPLL0_50M   41
+#defineCLK_DPLL1_50M   42
+#defineCLK_CPPLL_50M   43
+#defineCLK_M0_39M  44
+#defineCLK_M1_63M  45
+#define CLK_PLL_NUM(CLK_M1_63M + 1)
+
+
+#defineCLK_AP_APB  0
+#defineCLK_AP_USB3 1
+#defineCLK_UART0   2
+#defineCLK_UART1   3
+#defineCLK_UART2   4
+#defineCLK_UART3   5
+#defineCLK_UART4   6
+#defineCLK_I2C07
+#defineCLK_I2C18
+#defineCLK_I2C29
+#defineCLK_I2C310
+#defineCLK_I2C411
+#defineCLK_I2C512
+#defineCLK_SPI013
+#defineCLK_SPI114
+#defineCLK_SPI215
+#defineCLK_SPI316
+#defineCLK_IIS017
+#defineCLK_IIS118
+#defineCLK_IIS219
+#defineCLK_IIS320
+#define CLK_AP_CLK_NUM (CLK_IIS3 + 1)
+
+#defineCLK_AON_APB 0
+#defineCLK_AUX01
+#defineCLK_AUX12
+#defineCLK_AUX2