subject:"\[PATCH V4 10\/12\] clk\: sprd\: add clocks support for SC9860"

[PATCH V4 10/12] clk: sprd: add clocks support for SC9860

2017-11-09 Thread Chunyan Zhang

This patch added the list of clocks for Spreadtrum's SC9860 SoC,
together with clock initialization code.

Signed-off-by: Chunyan Zhang 
---
 drivers/clk/sprd/Kconfig  |   10 +
 drivers/clk/sprd/Makefile |3 +
 drivers/clk/sprd/sc9860-clk.c | 1987 +
 3 files changed, 2000 insertions(+)
 create mode 100644 drivers/clk/sprd/sc9860-clk.c

diff --git a/drivers/clk/sprd/Kconfig b/drivers/clk/sprd/Kconfig
index 67a3287..8789247 100644
--- a/drivers/clk/sprd/Kconfig
+++ b/drivers/clk/sprd/Kconfig
@@ -2,3 +2,13 @@ config SPRD_COMMON_CLK
tristate "Clock support for Spreadtrum SoCs"
depends on ARCH_SPRD || COMPILE_TEST
default ARCH_SPRD
+
+if SPRD_COMMON_CLK
+
+# SoC Drivers
+
+config SPRD_SC9860_CLK
+   tristate "Support for the Spreadtrum SC9860 clocks"
+   depends on (ARM64 && ARCH_SPRD) || COMPILE_TEST
+   default ARM64 && ARCH_SPRD
+endif
diff --git a/drivers/clk/sprd/Makefile b/drivers/clk/sprd/Makefile
index d693969..b0d81e5 100644
--- a/drivers/clk/sprd/Makefile
+++ b/drivers/clk/sprd/Makefile
@@ -6,3 +6,6 @@ clk-sprd-y  += mux.o
 clk-sprd-y += div.o
 clk-sprd-y += composite.o
 clk-sprd-y += pll.o
+
+## SoC support
+obj-$(CONFIG_SPRD_SC9860_CLK)  += sc9860-clk.o
diff --git a/drivers/clk/sprd/sc9860-clk.c b/drivers/clk/sprd/sc9860-clk.c
new file mode 100644
index 000..caf7194
--- /dev/null
+++ b/drivers/clk/sprd/sc9860-clk.c
@@ -0,0 +1,1987 @@
+/*
+ * Spreatrum SC9860 clock driver
+ *
+ * Copyright (C) 2017 Spreadtrum, Inc.
+ * Author: Chunyan Zhang 
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#include "common.h"
+#include "composite.h"
+#include "div.h"
+#include "gate.h"
+#include "mux.h"
+#include "pll.h"
+
+static CLK_FIXED_RATE(ext_rco_100m, "ext-rco-100m", 0, 1, 0);
+static CLK_FIXED_RATE(ext_32k, "ext-32k", 0, 32768, 0);
+
+static CLK_FIXED_FACTOR(fac_4m,"fac-4m",   "ext-26m",
+   6, 1, 0);
+static CLK_FIXED_FACTOR(fac_2m,"fac-2m",   "ext-26m",
+   13, 1, 0);
+static CLK_FIXED_FACTOR(fac_1m,"fac-1m",   "ext-26m",
+   26, 1, 0);
+static CLK_FIXED_FACTOR(fac_250k,  "fac-250k", "ext-26m",
+   104, 1, 0);
+static CLK_FIXED_FACTOR(fac_rpll0_26m, "rpll0-26m","ext-26m",
+   1, 1, 0);
+static CLK_FIXED_FACTOR(fac_rpll1_26m, "rpll1-26m","ext-26m",
+   1, 1, 0);
+static CLK_FIXED_FACTOR(fac_rco_25m,   "rco-25m",  "ext-rc0-100m",
+   4, 1, 0);
+static CLK_FIXED_FACTOR(fac_rco_4m,"rco-4m",   "ext-rc0-100m",
+   25, 1, 0);
+static CLK_FIXED_FACTOR(fac_rco_2m,"rco-2m",   "ext-rc0-100m",
+   50, 1, 0);
+static CLK_FIXED_FACTOR(fac_3k2,   "fac-3k2",  "ext-32k",
+   10, 1, 0);
+static CLK_FIXED_FACTOR(fac_1k,"fac-1k",   "ext-32k",
+   32, 1, 0);
+
+static SPRD_SC_GATE_CLK(mpll0_gate,"mpll0-gate",   "ext-26m", 0xb0,
+0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(mpll1_gate,"mpll1-gate",   "ext-26m", 0xb0,
+0x1000, BIT(18), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(dpll0_gate,"dpll0-gate",   "ext-26m", 0xb4,
+0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(dpll1_gate,"dpll1-gate",   "ext-26m", 0xb4,
+0x1000, BIT(18), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(ltepll0_gate,  "ltepll0-gate", "ext-26m", 0xb8,
+0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(twpll_gate,"twpll-gate",   "ext-26m", 0xbc,
+0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(ltepll1_gate,  "ltepll1-gate", "ext-26m", 0x10c,
+0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(rpll0_gate,"rpll0-gate",   "ext-26m", 0x16c,
+0x1000, BIT(2), 0, 0);
+static SPRD_SC_GATE_CLK(rpll1_gate,"rpll1-gate",   "ext-26m", 0x16c,
+0x1000, BIT(18), 0, 0);
+static SPRD_SC_GATE_CLK(cppll_gate,"cppll-gate",   "ext-26m", 0x2b4,
+0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(gpll_gate, "gpll-gate","ext-26m", 0x32c,
+   0x1000, BIT(0), CLK_IGNORE_UNUSED, CLK_GATE_SET_TO_DISABLE);
+
+static struct sprd_clk_common *sc9860_pmu_gate_clks[] = {
+   /* address base is 0x402b */
+   _gate.common,
+   _gate.common,
+   _gate.common,
+   _gate.common,
+   _gate.common,
+   _gate.common,
+   _gate.common,
+   _gate.common,
+   _gate.common,
+   _gate.common,
+   _gate.common,

[PATCH V4 10/12] clk: sprd: add clocks support for SC9860

2017-11-09 Thread Chunyan Zhang

This patch added the list of clocks for Spreadtrum's SC9860 SoC,
together with clock initialization code.

Signed-off-by: Chunyan Zhang 
---
 drivers/clk/sprd/Kconfig  |   10 +
 drivers/clk/sprd/Makefile |3 +
 drivers/clk/sprd/sc9860-clk.c | 1987 +
 3 files changed, 2000 insertions(+)
 create mode 100644 drivers/clk/sprd/sc9860-clk.c

diff --git a/drivers/clk/sprd/Kconfig b/drivers/clk/sprd/Kconfig
index 67a3287..8789247 100644
--- a/drivers/clk/sprd/Kconfig
+++ b/drivers/clk/sprd/Kconfig
@@ -2,3 +2,13 @@ config SPRD_COMMON_CLK
tristate "Clock support for Spreadtrum SoCs"
depends on ARCH_SPRD || COMPILE_TEST
default ARCH_SPRD
+
+if SPRD_COMMON_CLK
+
+# SoC Drivers
+
+config SPRD_SC9860_CLK
+   tristate "Support for the Spreadtrum SC9860 clocks"
+   depends on (ARM64 && ARCH_SPRD) || COMPILE_TEST
+   default ARM64 && ARCH_SPRD
+endif
diff --git a/drivers/clk/sprd/Makefile b/drivers/clk/sprd/Makefile
index d693969..b0d81e5 100644
--- a/drivers/clk/sprd/Makefile
+++ b/drivers/clk/sprd/Makefile
@@ -6,3 +6,6 @@ clk-sprd-y  += mux.o
 clk-sprd-y += div.o
 clk-sprd-y += composite.o
 clk-sprd-y += pll.o
+
+## SoC support
+obj-$(CONFIG_SPRD_SC9860_CLK)  += sc9860-clk.o
diff --git a/drivers/clk/sprd/sc9860-clk.c b/drivers/clk/sprd/sc9860-clk.c
new file mode 100644
index 000..caf7194
--- /dev/null
+++ b/drivers/clk/sprd/sc9860-clk.c
@@ -0,0 +1,1987 @@
+/*
+ * Spreatrum SC9860 clock driver
+ *
+ * Copyright (C) 2017 Spreadtrum, Inc.
+ * Author: Chunyan Zhang 
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#include "common.h"
+#include "composite.h"
+#include "div.h"
+#include "gate.h"
+#include "mux.h"
+#include "pll.h"
+
+static CLK_FIXED_RATE(ext_rco_100m, "ext-rco-100m", 0, 1, 0);
+static CLK_FIXED_RATE(ext_32k, "ext-32k", 0, 32768, 0);
+
+static CLK_FIXED_FACTOR(fac_4m,"fac-4m",   "ext-26m",
+   6, 1, 0);
+static CLK_FIXED_FACTOR(fac_2m,"fac-2m",   "ext-26m",
+   13, 1, 0);
+static CLK_FIXED_FACTOR(fac_1m,"fac-1m",   "ext-26m",
+   26, 1, 0);
+static CLK_FIXED_FACTOR(fac_250k,  "fac-250k", "ext-26m",
+   104, 1, 0);
+static CLK_FIXED_FACTOR(fac_rpll0_26m, "rpll0-26m","ext-26m",
+   1, 1, 0);
+static CLK_FIXED_FACTOR(fac_rpll1_26m, "rpll1-26m","ext-26m",
+   1, 1, 0);
+static CLK_FIXED_FACTOR(fac_rco_25m,   "rco-25m",  "ext-rc0-100m",
+   4, 1, 0);
+static CLK_FIXED_FACTOR(fac_rco_4m,"rco-4m",   "ext-rc0-100m",
+   25, 1, 0);
+static CLK_FIXED_FACTOR(fac_rco_2m,"rco-2m",   "ext-rc0-100m",
+   50, 1, 0);
+static CLK_FIXED_FACTOR(fac_3k2,   "fac-3k2",  "ext-32k",
+   10, 1, 0);
+static CLK_FIXED_FACTOR(fac_1k,"fac-1k",   "ext-32k",
+   32, 1, 0);
+
+static SPRD_SC_GATE_CLK(mpll0_gate,"mpll0-gate",   "ext-26m", 0xb0,
+0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(mpll1_gate,"mpll1-gate",   "ext-26m", 0xb0,
+0x1000, BIT(18), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(dpll0_gate,"dpll0-gate",   "ext-26m", 0xb4,
+0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(dpll1_gate,"dpll1-gate",   "ext-26m", 0xb4,
+0x1000, BIT(18), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(ltepll0_gate,  "ltepll0-gate", "ext-26m", 0xb8,
+0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(twpll_gate,"twpll-gate",   "ext-26m", 0xbc,
+0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(ltepll1_gate,  "ltepll1-gate", "ext-26m", 0x10c,
+0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(rpll0_gate,"rpll0-gate",   "ext-26m", 0x16c,
+0x1000, BIT(2), 0, 0);
+static SPRD_SC_GATE_CLK(rpll1_gate,"rpll1-gate",   "ext-26m", 0x16c,
+0x1000, BIT(18), 0, 0);
+static SPRD_SC_GATE_CLK(cppll_gate,"cppll-gate",   "ext-26m", 0x2b4,
+0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);
+static SPRD_SC_GATE_CLK(gpll_gate, "gpll-gate","ext-26m", 0x32c,
+   0x1000, BIT(0), CLK_IGNORE_UNUSED, CLK_GATE_SET_TO_DISABLE);
+
+static struct sprd_clk_common *sc9860_pmu_gate_clks[] = {
+   /* address base is 0x402b */
+   _gate.common,
+   _gate.common,
+   _gate.common,
+   _gate.common,
+   _gate.common,
+   _gate.common,
+   _gate.common,
+   _gate.common,
+   _gate.common,
+   _gate.common,
+   _gate.common,
+};
+
+static struct clk_hw_onecell_data sc9860_pmu_gate_hws

[PATCH V4 10/12] clk: sprd: add clocks support for SC9860

[PATCH V4 10/12] clk: sprd: add clocks support for SC9860

2 matches

Site Navigation

Mail list logo

Footer information