Thanks James for the review. Please see my inline answers.
On 7/23/2018 11:10 AM, James Feist wrote:
On 07/23/2018 10:48 AM, Jae Hyun Yoo wrote:
In most of cases, interrupt bits are set one by one but there are
also a lot of other cases that Aspeed I2C IP sends multiple
interrupt bits with
Thanks James for the review. Please see my inline answers.
On 7/23/2018 11:10 AM, James Feist wrote:
On 07/23/2018 10:48 AM, Jae Hyun Yoo wrote:
In most of cases, interrupt bits are set one by one but there are
also a lot of other cases that Aspeed I2C IP sends multiple
interrupt bits with
On 07/23/2018 10:48 AM, Jae Hyun Yoo wrote:
In most of cases, interrupt bits are set one by one but there are
also a lot of other cases that Aspeed I2C IP sends multiple
interrupt bits with combining master and slave events using a
single interrupt call. It happens much in multi-master
On 07/23/2018 10:48 AM, Jae Hyun Yoo wrote:
In most of cases, interrupt bits are set one by one but there are
also a lot of other cases that Aspeed I2C IP sends multiple
interrupt bits with combining master and slave events using a
single interrupt call. It happens much in multi-master
In most of cases, interrupt bits are set one by one but there are
also a lot of other cases that Aspeed I2C IP sends multiple
interrupt bits with combining master and slave events using a
single interrupt call. It happens much in multi-master environment
than single-master. For an example, when
In most of cases, interrupt bits are set one by one but there are
also a lot of other cases that Aspeed I2C IP sends multiple
interrupt bits with combining master and slave events using a
single interrupt call. It happens much in multi-master environment
than single-master. For an example, when
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