Re: [PATCH v1] clk: qcom: gdsc: Add support to poll CFG register to check GDSC state

2018-05-04 Thread Taniya Das 

Yeah sure Stephen.

On 5/5/2018 8:21 AM, Stephen Boyd wrote:

Quoting Taniya Das (2018-05-03 02:09:57)

Hello Stephen,

I have tested the below patch & didn't see any issues.


Alright. Thanks! Can I take that as a "Tested-by"?



--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation.

--

Re: [PATCH v1] clk: qcom: gdsc: Add support to poll CFG register to check GDSC state

2018-05-04 Thread Taniya Das 

Yeah sure Stephen.

On 5/5/2018 8:21 AM, Stephen Boyd wrote:

Quoting Taniya Das (2018-05-03 02:09:57)

Hello Stephen,

I have tested the below patch & didn't see any issues.


Alright. Thanks! Can I take that as a "Tested-by"?



--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation.

--

Re: [PATCH v1] clk: qcom: gdsc: Add support to poll CFG register to check GDSC state

2018-05-04 Thread Stephen Boyd 
Quoting Taniya Das (2018-05-03 02:09:57)
> Hello Stephen,
> 
> I have tested the below patch & didn't see any issues.

Alright. Thanks! Can I take that as a "Tested-by"?

Re: [PATCH v1] clk: qcom: gdsc: Add support to poll CFG register to check GDSC state

2018-05-04 Thread Stephen Boyd 
Quoting Taniya Das (2018-05-03 02:09:57)
> Hello Stephen,
> 
> I have tested the below patch & didn't see any issues.

Alright. Thanks! Can I take that as a "Tested-by"?

Re: [PATCH v1] clk: qcom: gdsc: Add support to poll CFG register to check GDSC state

2018-05-03 Thread Taniya Das 

Hello Stephen,

I have tested the below patch & didn't see any issues.

On 5/2/2018 12:27 PM, Stephen Boyd wrote:

Quoting Taniya Das (2018-04-30 22:03:33)

@@ -45,15 +50,28 @@

  #define domain_to_gdsc(domain) container_of(domain, struct gdsc, pd)

-static int gdsc_is_enabled(struct gdsc *sc, unsigned int reg)
+static int gdsc_is_enabled(struct gdsc *sc, bool en)
  {
+   unsigned int reg;
 u32 val;
 int ret;

+   if (sc->flags & POLL_CFG_GDSCR)
+   reg = sc->gdscr + CFG_GDSCR_OFFSET;
+   else
+   reg = sc->gds_hw_ctrl ? sc->gds_hw_ctrl : sc->gdscr;
+
 ret = regmap_read(sc->regmap, reg, );
 if (ret)
 return ret;

+   if (sc->flags & POLL_CFG_GDSCR) {
+   if (en)
+   return !!(val & GDSC_POWER_UP_COMPLETE);
+   else
+   return !(val & GDSC_POWER_DOWN_COMPLETE);


This is confusing, but also is correct, because this function is
returning if the gdsc is enabled or not, and that also happens to be
false when the gdsc is not enabled and this bit is set.


+   }
+
 return !!(val & PWR_ON_MASK);
  }

@@ -64,17 +82,17 @@ static int gdsc_hwctrl(struct gdsc *sc, bool en)
 return regmap_update_bits(sc->regmap, sc->gdscr, HW_CONTROL_MASK, val);
  }

-static int gdsc_poll_status(struct gdsc *sc, unsigned int reg, bool en)
+static int gdsc_poll_status(struct gdsc *sc, bool en)
  {
 ktime_t start;

 start = ktime_get();
 do {
-   if (gdsc_is_enabled(sc, reg) == en)
+   if (gdsc_is_enabled(sc, en) == en)


I still don't like this == en logic. How about this patch on top? If you
can test it out, I'll merge your patch and then my patch to make this
all easier to read. Note that I changed the off case for
POWER_DOWN_COMPLETE to be a double negation.

---8<---
diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c
index 2a6b0ff7d451..4696e241db89 100644
--- a/drivers/clk/qcom/gdsc.c
+++ b/drivers/clk/qcom/gdsc.c
@@ -50,7 +50,13 @@
  
  #define domain_to_gdsc(domain) container_of(domain, struct gdsc, pd)
  
-static int gdsc_is_enabled(struct gdsc *sc, bool en)

+enum gdsc_status {
+   GDSC_OFF,
+   GDSC_ON
+};
+
+/* Returns 1 if GDSC status is status, 0 if not, and < 0 on error */
+static int gdsc_check_status(struct gdsc *sc, enum gdsc_status status)
  {
unsigned int reg;
u32 val;
@@ -58,21 +64,32 @@ static int gdsc_is_enabled(struct gdsc *sc, bool en)
  
  	if (sc->flags & POLL_CFG_GDSCR)

reg = sc->gdscr + CFG_GDSCR_OFFSET;
+   else if (sc->gds_hw_ctrl)
+   reg = sc->gds_hw_ctrl;
else
-   reg = sc->gds_hw_ctrl ? sc->gds_hw_ctrl : sc->gdscr;
+   reg = sc->gdscr;
  
  	ret = regmap_read(sc->regmap, reg, );

if (ret)
return ret;
  
  	if (sc->flags & POLL_CFG_GDSCR) {

-   if (en)
+   switch (status) {
+   case GDSC_ON:
return !!(val & GDSC_POWER_UP_COMPLETE);
-   else
-   return !(val & GDSC_POWER_DOWN_COMPLETE);
+   case GDSC_OFF:
+   return !!(val & GDSC_POWER_DOWN_COMPLETE);
+   }
+   }
+
+   switch (status) {
+   case GDSC_ON:
+   return !!(val & PWR_ON_MASK);
+   case GDSC_OFF:
+   return !(val & PWR_ON_MASK);
}
  
-	return !!(val & PWR_ON_MASK);

+   return -EINVAL;
  }
  
  static int gdsc_hwctrl(struct gdsc *sc, bool en)

@@ -82,33 +99,33 @@ static int gdsc_hwctrl(struct gdsc *sc, bool en)
return regmap_update_bits(sc->regmap, sc->gdscr, HW_CONTROL_MASK, val);
  }
  
-static int gdsc_poll_status(struct gdsc *sc, bool en)

+static int gdsc_poll_status(struct gdsc *sc, enum gdsc_status status)
  {
ktime_t start;
  
  	start = ktime_get();

do {
-   if (gdsc_is_enabled(sc, en) == en)
+   if (gdsc_check_status(sc, status))
return 0;
} while (ktime_us_delta(ktime_get(), start) < TIMEOUT_US);
  
-	if (gdsc_is_enabled(sc, en) == en)

+   if (gdsc_check_status(sc, status))
return 0;
  
  	return -ETIMEDOUT;

  }
  
-static int gdsc_toggle_logic(struct gdsc *sc, bool en)

+static int gdsc_toggle_logic(struct gdsc *sc, enum gdsc_status status)
  {
int ret;
-   u32 val = en ? 0 : SW_COLLAPSE_MASK;
+   u32 val = (status == GDSC_ON) ? 0 : SW_COLLAPSE_MASK;
  
  	ret = regmap_update_bits(sc->regmap, sc->gdscr, SW_COLLAPSE_MASK, val);

if (ret)
return ret;
  
  	/* If disabling votable gdscs, don't poll on status */

-   if ((sc->flags & VOTABLE) && !en) {
+   if ((sc->flags & VOTABLE) && status == GDSC_OFF) {
/*
 * Add a short delay here to ensure that an enable
 * right after it was disabled does not put it in an
@@

Re: [PATCH v1] clk: qcom: gdsc: Add support to poll CFG register to check GDSC state

2018-05-03 Thread Taniya Das 

Hello Stephen,

I have tested the below patch & didn't see any issues.

On 5/2/2018 12:27 PM, Stephen Boyd wrote:

Quoting Taniya Das (2018-04-30 22:03:33)

@@ -45,15 +50,28 @@

  #define domain_to_gdsc(domain) container_of(domain, struct gdsc, pd)

-static int gdsc_is_enabled(struct gdsc *sc, unsigned int reg)
+static int gdsc_is_enabled(struct gdsc *sc, bool en)
  {
+   unsigned int reg;
 u32 val;
 int ret;

+   if (sc->flags & POLL_CFG_GDSCR)
+   reg = sc->gdscr + CFG_GDSCR_OFFSET;
+   else
+   reg = sc->gds_hw_ctrl ? sc->gds_hw_ctrl : sc->gdscr;
+
 ret = regmap_read(sc->regmap, reg, );
 if (ret)
 return ret;

+   if (sc->flags & POLL_CFG_GDSCR) {
+   if (en)
+   return !!(val & GDSC_POWER_UP_COMPLETE);
+   else
+   return !(val & GDSC_POWER_DOWN_COMPLETE);


This is confusing, but also is correct, because this function is
returning if the gdsc is enabled or not, and that also happens to be
false when the gdsc is not enabled and this bit is set.


+   }
+
 return !!(val & PWR_ON_MASK);
  }

@@ -64,17 +82,17 @@ static int gdsc_hwctrl(struct gdsc *sc, bool en)
 return regmap_update_bits(sc->regmap, sc->gdscr, HW_CONTROL_MASK, val);
  }

-static int gdsc_poll_status(struct gdsc *sc, unsigned int reg, bool en)
+static int gdsc_poll_status(struct gdsc *sc, bool en)
  {
 ktime_t start;

 start = ktime_get();
 do {
-   if (gdsc_is_enabled(sc, reg) == en)
+   if (gdsc_is_enabled(sc, en) == en)


I still don't like this == en logic. How about this patch on top? If you
can test it out, I'll merge your patch and then my patch to make this
all easier to read. Note that I changed the off case for
POWER_DOWN_COMPLETE to be a double negation.

---8<---
diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c
index 2a6b0ff7d451..4696e241db89 100644
--- a/drivers/clk/qcom/gdsc.c
+++ b/drivers/clk/qcom/gdsc.c
@@ -50,7 +50,13 @@
  
  #define domain_to_gdsc(domain) container_of(domain, struct gdsc, pd)
  
-static int gdsc_is_enabled(struct gdsc *sc, bool en)

+enum gdsc_status {
+   GDSC_OFF,
+   GDSC_ON
+};
+
+/* Returns 1 if GDSC status is status, 0 if not, and < 0 on error */
+static int gdsc_check_status(struct gdsc *sc, enum gdsc_status status)
  {
unsigned int reg;
u32 val;
@@ -58,21 +64,32 @@ static int gdsc_is_enabled(struct gdsc *sc, bool en)
  
  	if (sc->flags & POLL_CFG_GDSCR)

reg = sc->gdscr + CFG_GDSCR_OFFSET;
+   else if (sc->gds_hw_ctrl)
+   reg = sc->gds_hw_ctrl;
else
-   reg = sc->gds_hw_ctrl ? sc->gds_hw_ctrl : sc->gdscr;
+   reg = sc->gdscr;
  
  	ret = regmap_read(sc->regmap, reg, );

if (ret)
return ret;
  
  	if (sc->flags & POLL_CFG_GDSCR) {

-   if (en)
+   switch (status) {
+   case GDSC_ON:
return !!(val & GDSC_POWER_UP_COMPLETE);
-   else
-   return !(val & GDSC_POWER_DOWN_COMPLETE);
+   case GDSC_OFF:
+   return !!(val & GDSC_POWER_DOWN_COMPLETE);
+   }
+   }
+
+   switch (status) {
+   case GDSC_ON:
+   return !!(val & PWR_ON_MASK);
+   case GDSC_OFF:
+   return !(val & PWR_ON_MASK);
}
  
-	return !!(val & PWR_ON_MASK);

+   return -EINVAL;
  }
  
  static int gdsc_hwctrl(struct gdsc *sc, bool en)

@@ -82,33 +99,33 @@ static int gdsc_hwctrl(struct gdsc *sc, bool en)
return regmap_update_bits(sc->regmap, sc->gdscr, HW_CONTROL_MASK, val);
  }
  
-static int gdsc_poll_status(struct gdsc *sc, bool en)

+static int gdsc_poll_status(struct gdsc *sc, enum gdsc_status status)
  {
ktime_t start;
  
  	start = ktime_get();

do {
-   if (gdsc_is_enabled(sc, en) == en)
+   if (gdsc_check_status(sc, status))
return 0;
} while (ktime_us_delta(ktime_get(), start) < TIMEOUT_US);
  
-	if (gdsc_is_enabled(sc, en) == en)

+   if (gdsc_check_status(sc, status))
return 0;
  
  	return -ETIMEDOUT;

  }
  
-static int gdsc_toggle_logic(struct gdsc *sc, bool en)

+static int gdsc_toggle_logic(struct gdsc *sc, enum gdsc_status status)
  {
int ret;
-   u32 val = en ? 0 : SW_COLLAPSE_MASK;
+   u32 val = (status == GDSC_ON) ? 0 : SW_COLLAPSE_MASK;
  
  	ret = regmap_update_bits(sc->regmap, sc->gdscr, SW_COLLAPSE_MASK, val);

if (ret)
return ret;
  
  	/* If disabling votable gdscs, don't poll on status */

-   if ((sc->flags & VOTABLE) && !en) {
+   if ((sc->flags & VOTABLE) && status == GDSC_OFF) {
/*
 * Add a short delay here to ensure that an enable
 * right after it was disabled does not put it in an
@@

Re: [PATCH v1] clk: qcom: gdsc: Add support to poll CFG register to check GDSC state

2018-05-02 Thread Stephen Boyd 
Quoting Taniya Das (2018-04-30 22:03:33)
> @@ -45,15 +50,28 @@
> 
>  #define domain_to_gdsc(domain) container_of(domain, struct gdsc, pd)
> 
> -static int gdsc_is_enabled(struct gdsc *sc, unsigned int reg)
> +static int gdsc_is_enabled(struct gdsc *sc, bool en)
>  {
> +   unsigned int reg;
> u32 val;
> int ret;
> 
> +   if (sc->flags & POLL_CFG_GDSCR)
> +   reg = sc->gdscr + CFG_GDSCR_OFFSET;
> +   else
> +   reg = sc->gds_hw_ctrl ? sc->gds_hw_ctrl : sc->gdscr;
> +
> ret = regmap_read(sc->regmap, reg, );
> if (ret)
> return ret;
> 
> +   if (sc->flags & POLL_CFG_GDSCR) {
> +   if (en)
> +   return !!(val & GDSC_POWER_UP_COMPLETE);
> +   else
> +   return !(val & GDSC_POWER_DOWN_COMPLETE);

This is confusing, but also is correct, because this function is
returning if the gdsc is enabled or not, and that also happens to be
false when the gdsc is not enabled and this bit is set.

> +   }
> +
> return !!(val & PWR_ON_MASK);
>  }
> 
> @@ -64,17 +82,17 @@ static int gdsc_hwctrl(struct gdsc *sc, bool en)
> return regmap_update_bits(sc->regmap, sc->gdscr, HW_CONTROL_MASK, 
> val);
>  }
> 
> -static int gdsc_poll_status(struct gdsc *sc, unsigned int reg, bool en)
> +static int gdsc_poll_status(struct gdsc *sc, bool en)
>  {
> ktime_t start;
> 
> start = ktime_get();
> do {
> -   if (gdsc_is_enabled(sc, reg) == en)
> +   if (gdsc_is_enabled(sc, en) == en)

I still don't like this == en logic. How about this patch on top? If you
can test it out, I'll merge your patch and then my patch to make this
all easier to read. Note that I changed the off case for
POWER_DOWN_COMPLETE to be a double negation.

---8<---
diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c
index 2a6b0ff7d451..4696e241db89 100644
--- a/drivers/clk/qcom/gdsc.c
+++ b/drivers/clk/qcom/gdsc.c
@@ -50,7 +50,13 @@
 
 #define domain_to_gdsc(domain) container_of(domain, struct gdsc, pd)
 
-static int gdsc_is_enabled(struct gdsc *sc, bool en)
+enum gdsc_status {
+   GDSC_OFF,
+   GDSC_ON
+};
+
+/* Returns 1 if GDSC status is status, 0 if not, and < 0 on error */
+static int gdsc_check_status(struct gdsc *sc, enum gdsc_status status)
 {
unsigned int reg;
u32 val;
@@ -58,21 +64,32 @@ static int gdsc_is_enabled(struct gdsc *sc, bool en)
 
if (sc->flags & POLL_CFG_GDSCR)
reg = sc->gdscr + CFG_GDSCR_OFFSET;
+   else if (sc->gds_hw_ctrl)
+   reg = sc->gds_hw_ctrl;
else
-   reg = sc->gds_hw_ctrl ? sc->gds_hw_ctrl : sc->gdscr;
+   reg = sc->gdscr;
 
ret = regmap_read(sc->regmap, reg, );
if (ret)
return ret;
 
if (sc->flags & POLL_CFG_GDSCR) {
-   if (en)
+   switch (status) {
+   case GDSC_ON:
return !!(val & GDSC_POWER_UP_COMPLETE);
-   else
-   return !(val & GDSC_POWER_DOWN_COMPLETE);
+   case GDSC_OFF:
+   return !!(val & GDSC_POWER_DOWN_COMPLETE);
+   }
+   }
+
+   switch (status) {
+   case GDSC_ON:
+   return !!(val & PWR_ON_MASK);
+   case GDSC_OFF:
+   return !(val & PWR_ON_MASK);
}
 
-   return !!(val & PWR_ON_MASK);
+   return -EINVAL;
 }
 
 static int gdsc_hwctrl(struct gdsc *sc, bool en)
@@ -82,33 +99,33 @@ static int gdsc_hwctrl(struct gdsc *sc, bool en)
return regmap_update_bits(sc->regmap, sc->gdscr, HW_CONTROL_MASK, val);
 }
 
-static int gdsc_poll_status(struct gdsc *sc, bool en)
+static int gdsc_poll_status(struct gdsc *sc, enum gdsc_status status)
 {
ktime_t start;
 
start = ktime_get();
do {
-   if (gdsc_is_enabled(sc, en) == en)
+   if (gdsc_check_status(sc, status))
return 0;
} while (ktime_us_delta(ktime_get(), start) < TIMEOUT_US);
 
-   if (gdsc_is_enabled(sc, en) == en)
+   if (gdsc_check_status(sc, status))
return 0;
 
return -ETIMEDOUT;
 }
 
-static int gdsc_toggle_logic(struct gdsc *sc, bool en)
+static int gdsc_toggle_logic(struct gdsc *sc, enum gdsc_status status)
 {
int ret;
-   u32 val = en ? 0 : SW_COLLAPSE_MASK;
+   u32 val = (status == GDSC_ON) ? 0 : SW_COLLAPSE_MASK;
 
ret = regmap_update_bits(sc->regmap, sc->gdscr, SW_COLLAPSE_MASK, val);
if (ret)
return ret;
 
/* If disabling votable gdscs, don't poll on status */
-   if ((sc->flags & VOTABLE) && !en) {
+   if ((sc->flags & VOTABLE) && status == GDSC_OFF) {
/*
 * Add a short delay here to ensure that an enable
 * right after it was disabled does not put it in an
@@ -118,7 +135,7 @@ static int

Re: [PATCH v1] clk: qcom: gdsc: Add support to poll CFG register to check GDSC state

2018-05-02 Thread Stephen Boyd 
Quoting Taniya Das (2018-04-30 22:03:33)
> @@ -45,15 +50,28 @@
> 
>  #define domain_to_gdsc(domain) container_of(domain, struct gdsc, pd)
> 
> -static int gdsc_is_enabled(struct gdsc *sc, unsigned int reg)
> +static int gdsc_is_enabled(struct gdsc *sc, bool en)
>  {
> +   unsigned int reg;
> u32 val;
> int ret;
> 
> +   if (sc->flags & POLL_CFG_GDSCR)
> +   reg = sc->gdscr + CFG_GDSCR_OFFSET;
> +   else
> +   reg = sc->gds_hw_ctrl ? sc->gds_hw_ctrl : sc->gdscr;
> +
> ret = regmap_read(sc->regmap, reg, );
> if (ret)
> return ret;
> 
> +   if (sc->flags & POLL_CFG_GDSCR) {
> +   if (en)
> +   return !!(val & GDSC_POWER_UP_COMPLETE);
> +   else
> +   return !(val & GDSC_POWER_DOWN_COMPLETE);

This is confusing, but also is correct, because this function is
returning if the gdsc is enabled or not, and that also happens to be
false when the gdsc is not enabled and this bit is set.

> +   }
> +
> return !!(val & PWR_ON_MASK);
>  }
> 
> @@ -64,17 +82,17 @@ static int gdsc_hwctrl(struct gdsc *sc, bool en)
> return regmap_update_bits(sc->regmap, sc->gdscr, HW_CONTROL_MASK, 
> val);
>  }
> 
> -static int gdsc_poll_status(struct gdsc *sc, unsigned int reg, bool en)
> +static int gdsc_poll_status(struct gdsc *sc, bool en)
>  {
> ktime_t start;
> 
> start = ktime_get();
> do {
> -   if (gdsc_is_enabled(sc, reg) == en)
> +   if (gdsc_is_enabled(sc, en) == en)

I still don't like this == en logic. How about this patch on top? If you
can test it out, I'll merge your patch and then my patch to make this
all easier to read. Note that I changed the off case for
POWER_DOWN_COMPLETE to be a double negation.

---8<---
diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c
index 2a6b0ff7d451..4696e241db89 100644
--- a/drivers/clk/qcom/gdsc.c
+++ b/drivers/clk/qcom/gdsc.c
@@ -50,7 +50,13 @@
 
 #define domain_to_gdsc(domain) container_of(domain, struct gdsc, pd)
 
-static int gdsc_is_enabled(struct gdsc *sc, bool en)
+enum gdsc_status {
+   GDSC_OFF,
+   GDSC_ON
+};
+
+/* Returns 1 if GDSC status is status, 0 if not, and < 0 on error */
+static int gdsc_check_status(struct gdsc *sc, enum gdsc_status status)
 {
unsigned int reg;
u32 val;
@@ -58,21 +64,32 @@ static int gdsc_is_enabled(struct gdsc *sc, bool en)
 
if (sc->flags & POLL_CFG_GDSCR)
reg = sc->gdscr + CFG_GDSCR_OFFSET;
+   else if (sc->gds_hw_ctrl)
+   reg = sc->gds_hw_ctrl;
else
-   reg = sc->gds_hw_ctrl ? sc->gds_hw_ctrl : sc->gdscr;
+   reg = sc->gdscr;
 
ret = regmap_read(sc->regmap, reg, );
if (ret)
return ret;
 
if (sc->flags & POLL_CFG_GDSCR) {
-   if (en)
+   switch (status) {
+   case GDSC_ON:
return !!(val & GDSC_POWER_UP_COMPLETE);
-   else
-   return !(val & GDSC_POWER_DOWN_COMPLETE);
+   case GDSC_OFF:
+   return !!(val & GDSC_POWER_DOWN_COMPLETE);
+   }
+   }
+
+   switch (status) {
+   case GDSC_ON:
+   return !!(val & PWR_ON_MASK);
+   case GDSC_OFF:
+   return !(val & PWR_ON_MASK);
}
 
-   return !!(val & PWR_ON_MASK);
+   return -EINVAL;
 }
 
 static int gdsc_hwctrl(struct gdsc *sc, bool en)
@@ -82,33 +99,33 @@ static int gdsc_hwctrl(struct gdsc *sc, bool en)
return regmap_update_bits(sc->regmap, sc->gdscr, HW_CONTROL_MASK, val);
 }
 
-static int gdsc_poll_status(struct gdsc *sc, bool en)
+static int gdsc_poll_status(struct gdsc *sc, enum gdsc_status status)
 {
ktime_t start;
 
start = ktime_get();
do {
-   if (gdsc_is_enabled(sc, en) == en)
+   if (gdsc_check_status(sc, status))
return 0;
} while (ktime_us_delta(ktime_get(), start) < TIMEOUT_US);
 
-   if (gdsc_is_enabled(sc, en) == en)
+   if (gdsc_check_status(sc, status))
return 0;
 
return -ETIMEDOUT;
 }
 
-static int gdsc_toggle_logic(struct gdsc *sc, bool en)
+static int gdsc_toggle_logic(struct gdsc *sc, enum gdsc_status status)
 {
int ret;
-   u32 val = en ? 0 : SW_COLLAPSE_MASK;
+   u32 val = (status == GDSC_ON) ? 0 : SW_COLLAPSE_MASK;
 
ret = regmap_update_bits(sc->regmap, sc->gdscr, SW_COLLAPSE_MASK, val);
if (ret)
return ret;
 
/* If disabling votable gdscs, don't poll on status */
-   if ((sc->flags & VOTABLE) && !en) {
+   if ((sc->flags & VOTABLE) && status == GDSC_OFF) {
/*
 * Add a short delay here to ensure that an enable
 * right after it was disabled does not put it in an
@@ -118,7 +135,7 @@ static int

[PATCH v1] clk: qcom: gdsc: Add support to poll CFG register to check GDSC state

2018-04-30 Thread Taniya Das 
From: Amit Nischal 

The default behavior of the GDSC enable/disable sequence is to
poll the status bits of either the actual GDSCR or the
corresponding HW_CTRL registers.

On targets which have support for a CFG_GDSCR register, the
status bits might not show the correct state of the GDSC,
especially in the disable sequence, where the status bit
will be cleared even before the core is completely power
collapsed. On targets with this issue, poll the power on/off
bits in the CFG_GDSCR register instead to correctly determine
the GDSC state.

Signed-off-by: Amit Nischal 
Signed-off-by: Taniya Das 
---
 drivers/clk/qcom/gdsc.c | 42 ++
 drivers/clk/qcom/gdsc.h |  1 +
 2 files changed, 27 insertions(+), 16 deletions(-)

diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c
index cb61c15..2a6b0ff 100644
--- a/drivers/clk/qcom/gdsc.c
+++ b/drivers/clk/qcom/gdsc.c
@@ -33,6 +33,11 @@
 #define GMEM_CLAMP_IO_MASK BIT(0)
 #define GMEM_RESET_MASKBIT(4)

+/* CFG_GDSCR */
+#define GDSC_POWER_UP_COMPLETE BIT(16)
+#define GDSC_POWER_DOWN_COMPLETE   BIT(15)
+#define CFG_GDSCR_OFFSET   0x4
+
 /* Wait 2^n CXO cycles between all states. Here, n=2 (4 cycles). */
 #define EN_REST_WAIT_VAL   (0x2 << 20)
 #define EN_FEW_WAIT_VAL(0x8 << 16)
@@ -45,15 +50,28 @@

 #define domain_to_gdsc(domain) container_of(domain, struct gdsc, pd)

-static int gdsc_is_enabled(struct gdsc *sc, unsigned int reg)
+static int gdsc_is_enabled(struct gdsc *sc, bool en)
 {
+   unsigned int reg;
u32 val;
int ret;

+   if (sc->flags & POLL_CFG_GDSCR)
+   reg = sc->gdscr + CFG_GDSCR_OFFSET;
+   else
+   reg = sc->gds_hw_ctrl ? sc->gds_hw_ctrl : sc->gdscr;
+
ret = regmap_read(sc->regmap, reg, );
if (ret)
return ret;

+   if (sc->flags & POLL_CFG_GDSCR) {
+   if (en)
+   return !!(val & GDSC_POWER_UP_COMPLETE);
+   else
+   return !(val & GDSC_POWER_DOWN_COMPLETE);
+   }
+
return !!(val & PWR_ON_MASK);
 }

@@ -64,17 +82,17 @@ static int gdsc_hwctrl(struct gdsc *sc, bool en)
return regmap_update_bits(sc->regmap, sc->gdscr, HW_CONTROL_MASK, val);
 }

-static int gdsc_poll_status(struct gdsc *sc, unsigned int reg, bool en)
+static int gdsc_poll_status(struct gdsc *sc, bool en)
 {
ktime_t start;

start = ktime_get();
do {
-   if (gdsc_is_enabled(sc, reg) == en)
+   if (gdsc_is_enabled(sc, en) == en)
return 0;
} while (ktime_us_delta(ktime_get(), start) < TIMEOUT_US);

-   if (gdsc_is_enabled(sc, reg) == en)
+   if (gdsc_is_enabled(sc, en) == en)
return 0;

return -ETIMEDOUT;
@@ -84,7 +102,6 @@ static int gdsc_toggle_logic(struct gdsc *sc, bool en)
 {
int ret;
u32 val = en ? 0 : SW_COLLAPSE_MASK;
-   unsigned int status_reg = sc->gdscr;

ret = regmap_update_bits(sc->regmap, sc->gdscr, SW_COLLAPSE_MASK, val);
if (ret)
@@ -101,8 +118,7 @@ static int gdsc_toggle_logic(struct gdsc *sc, bool en)
return 0;
}

-   if (sc->gds_hw_ctrl) {
-   status_reg = sc->gds_hw_ctrl;
+   if (sc->gds_hw_ctrl)
/*
 * The gds hw controller asserts/de-asserts the status bit soon
 * after it receives a power on/off request from a master.
@@ -114,9 +130,8 @@ static int gdsc_toggle_logic(struct gdsc *sc, bool en)
 * and polling the status bit.
 */
udelay(1);
-   }

-   return gdsc_poll_status(sc, status_reg, en);
+   return gdsc_poll_status(sc, en);
 }

 static inline int gdsc_deassert_reset(struct gdsc *sc)
@@ -240,8 +255,6 @@ static int gdsc_disable(struct generic_pm_domain *domain)

/* Turn off HW trigger mode if supported */
if (sc->flags & HW_CTRL) {
-   unsigned int reg;
-
ret = gdsc_hwctrl(sc, false);
if (ret < 0)
return ret;
@@ -253,8 +266,7 @@ static int gdsc_disable(struct generic_pm_domain *domain)
 */
udelay(1);

-   reg = sc->gds_hw_ctrl ? sc->gds_hw_ctrl : sc->gdscr;
-   ret = gdsc_poll_status(sc, reg, true);
+   ret = gdsc_poll_status(sc, true);
if (ret)
return ret;
}
@@ -276,7 +288,6 @@ static int gdsc_init(struct gdsc *sc)
 {
u32 mask, val;
int on, ret;
-   unsigned int reg;

/*
 * Disable HW trigger: collapse/restore occur based on registers writes.
@@ -297,8 +308,7 @@ static int gdsc_init(struct gdsc *sc)
return ret;
}

-   reg = sc->gds_hw_ctrl ? sc->gds_hw_ctrl :

[PATCH v1] clk: qcom: gdsc: Add support to poll CFG register to check GDSC state

2018-04-30 Thread Taniya Das 
From: Amit Nischal 

The default behavior of the GDSC enable/disable sequence is to
poll the status bits of either the actual GDSCR or the
corresponding HW_CTRL registers.

On targets which have support for a CFG_GDSCR register, the
status bits might not show the correct state of the GDSC,
especially in the disable sequence, where the status bit
will be cleared even before the core is completely power
collapsed. On targets with this issue, poll the power on/off
bits in the CFG_GDSCR register instead to correctly determine
the GDSC state.

Signed-off-by: Amit Nischal 
Signed-off-by: Taniya Das 
---
 drivers/clk/qcom/gdsc.c | 42 ++
 drivers/clk/qcom/gdsc.h |  1 +
 2 files changed, 27 insertions(+), 16 deletions(-)

diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c
index cb61c15..2a6b0ff 100644
--- a/drivers/clk/qcom/gdsc.c
+++ b/drivers/clk/qcom/gdsc.c
@@ -33,6 +33,11 @@
 #define GMEM_CLAMP_IO_MASK BIT(0)
 #define GMEM_RESET_MASKBIT(4)

+/* CFG_GDSCR */
+#define GDSC_POWER_UP_COMPLETE BIT(16)
+#define GDSC_POWER_DOWN_COMPLETE   BIT(15)
+#define CFG_GDSCR_OFFSET   0x4
+
 /* Wait 2^n CXO cycles between all states. Here, n=2 (4 cycles). */
 #define EN_REST_WAIT_VAL   (0x2 << 20)
 #define EN_FEW_WAIT_VAL(0x8 << 16)
@@ -45,15 +50,28 @@

 #define domain_to_gdsc(domain) container_of(domain, struct gdsc, pd)

-static int gdsc_is_enabled(struct gdsc *sc, unsigned int reg)
+static int gdsc_is_enabled(struct gdsc *sc, bool en)
 {
+   unsigned int reg;
u32 val;
int ret;

+   if (sc->flags & POLL_CFG_GDSCR)
+   reg = sc->gdscr + CFG_GDSCR_OFFSET;
+   else
+   reg = sc->gds_hw_ctrl ? sc->gds_hw_ctrl : sc->gdscr;
+
ret = regmap_read(sc->regmap, reg, );
if (ret)
return ret;

+   if (sc->flags & POLL_CFG_GDSCR) {
+   if (en)
+   return !!(val & GDSC_POWER_UP_COMPLETE);
+   else
+   return !(val & GDSC_POWER_DOWN_COMPLETE);
+   }
+
return !!(val & PWR_ON_MASK);
 }

@@ -64,17 +82,17 @@ static int gdsc_hwctrl(struct gdsc *sc, bool en)
return regmap_update_bits(sc->regmap, sc->gdscr, HW_CONTROL_MASK, val);
 }

-static int gdsc_poll_status(struct gdsc *sc, unsigned int reg, bool en)
+static int gdsc_poll_status(struct gdsc *sc, bool en)
 {
ktime_t start;

start = ktime_get();
do {
-   if (gdsc_is_enabled(sc, reg) == en)
+   if (gdsc_is_enabled(sc, en) == en)
return 0;
} while (ktime_us_delta(ktime_get(), start) < TIMEOUT_US);

-   if (gdsc_is_enabled(sc, reg) == en)
+   if (gdsc_is_enabled(sc, en) == en)
return 0;

return -ETIMEDOUT;
@@ -84,7 +102,6 @@ static int gdsc_toggle_logic(struct gdsc *sc, bool en)
 {
int ret;
u32 val = en ? 0 : SW_COLLAPSE_MASK;
-   unsigned int status_reg = sc->gdscr;

ret = regmap_update_bits(sc->regmap, sc->gdscr, SW_COLLAPSE_MASK, val);
if (ret)
@@ -101,8 +118,7 @@ static int gdsc_toggle_logic(struct gdsc *sc, bool en)
return 0;
}

-   if (sc->gds_hw_ctrl) {
-   status_reg = sc->gds_hw_ctrl;
+   if (sc->gds_hw_ctrl)
/*
 * The gds hw controller asserts/de-asserts the status bit soon
 * after it receives a power on/off request from a master.
@@ -114,9 +130,8 @@ static int gdsc_toggle_logic(struct gdsc *sc, bool en)
 * and polling the status bit.
 */
udelay(1);
-   }

-   return gdsc_poll_status(sc, status_reg, en);
+   return gdsc_poll_status(sc, en);
 }

 static inline int gdsc_deassert_reset(struct gdsc *sc)
@@ -240,8 +255,6 @@ static int gdsc_disable(struct generic_pm_domain *domain)

/* Turn off HW trigger mode if supported */
if (sc->flags & HW_CTRL) {
-   unsigned int reg;
-
ret = gdsc_hwctrl(sc, false);
if (ret < 0)
return ret;
@@ -253,8 +266,7 @@ static int gdsc_disable(struct generic_pm_domain *domain)
 */
udelay(1);

-   reg = sc->gds_hw_ctrl ? sc->gds_hw_ctrl : sc->gdscr;
-   ret = gdsc_poll_status(sc, reg, true);
+   ret = gdsc_poll_status(sc, true);
if (ret)
return ret;
}
@@ -276,7 +288,6 @@ static int gdsc_init(struct gdsc *sc)
 {
u32 mask, val;
int on, ret;
-   unsigned int reg;

/*
 * Disable HW trigger: collapse/restore occur based on registers writes.
@@ -297,8 +308,7 @@ static int gdsc_init(struct gdsc *sc)
return ret;
}

-   reg = sc->gds_hw_ctrl ? sc->gds_hw_ctrl : sc->gdscr;
-   on = gdsc_is_enabled(sc, reg);
+   on =