Re: [PATCH v1 1/4] ARM: tegra: Fix missed EMC registers latching on resume from LP1 on Tegra30+

2018-11-19 Thread Jon Hunter
On 19/11/2018 21:27, Jon Hunter wrote: > > On 30/08/2018 19:54, Dmitry Osipenko wrote: >> The memory interface configuration and re-calibration interval are left >> unassigned on resume from LP1 because these registers are shadowed and >> require latching after being adjusted. >> >>

Re: [PATCH v1 1/4] ARM: tegra: Fix missed EMC registers latching on resume from LP1 on Tegra30+

2018-11-19 Thread Jon Hunter
On 19/11/2018 21:27, Jon Hunter wrote: > > On 30/08/2018 19:54, Dmitry Osipenko wrote: >> The memory interface configuration and re-calibration interval are left >> unassigned on resume from LP1 because these registers are shadowed and >> require latching after being adjusted. >> >>

Re: [PATCH v1 1/4] ARM: tegra: Fix missed EMC registers latching on resume from LP1 on Tegra30+

2018-11-19 Thread Jon Hunter
On 30/08/2018 19:54, Dmitry Osipenko wrote: > The memory interface configuration and re-calibration interval are left > unassigned on resume from LP1 because these registers are shadowed and > require latching after being adjusted. > > Signed-off-by: Dmitry Osipenko > --- >

Re: [PATCH v1 1/4] ARM: tegra: Fix missed EMC registers latching on resume from LP1 on Tegra30+

2018-11-19 Thread Jon Hunter
On 30/08/2018 19:54, Dmitry Osipenko wrote: > The memory interface configuration and re-calibration interval are left > unassigned on resume from LP1 because these registers are shadowed and > require latching after being adjusted. > > Signed-off-by: Dmitry Osipenko > --- >

[PATCH v1 1/4] ARM: tegra: Fix missed EMC registers latching on resume from LP1 on Tegra30+

2018-08-30 Thread Dmitry Osipenko
The memory interface configuration and re-calibration interval are left unassigned on resume from LP1 because these registers are shadowed and require latching after being adjusted. Signed-off-by: Dmitry Osipenko --- arch/arm/mach-tegra/sleep-tegra30.S | 2 ++ 1 file changed, 2 insertions(+)

[PATCH v1 1/4] ARM: tegra: Fix missed EMC registers latching on resume from LP1 on Tegra30+

2018-08-30 Thread Dmitry Osipenko
The memory interface configuration and re-calibration interval are left unassigned on resume from LP1 because these registers are shadowed and require latching after being adjusted. Signed-off-by: Dmitry Osipenko --- arch/arm/mach-tegra/sleep-tegra30.S | 2 ++ 1 file changed, 2 insertions(+)