RE: [PATCH v12 1/2] Documentation: DT: dma: Add Xilinx zynqmp dma device tree binding documentation

[Appana Durga Kedareswara Rao]

Hi Vinod,

> On Fri, Jul 01, 2016 at 05:07:05PM +0530, Kedareswara rao Appana wrote:
> > Device-tree binding documentation for Xilinx zynqmp dma engine used in
> > Zynq UltraScale+ MPSoC.
> 
> And I missed the cleanup part, so both applied  now

Thanks for applying the patches will send patch for the cleanup part
On top of this patch...

Regards,
Kedar.

> 
> --
> ~Vinod

RE: [PATCH v12 1/2] Documentation: DT: dma: Add Xilinx zynqmp dma device tree binding documentation

[Appana Durga Kedareswara Rao]

Hi Vinod,

> On Fri, Jul 01, 2016 at 05:07:05PM +0530, Kedareswara rao Appana wrote:
> > Device-tree binding documentation for Xilinx zynqmp dma engine used in
> > Zynq UltraScale+ MPSoC.
> 
> And I missed the cleanup part, so both applied  now

Thanks for applying the patches will send patch for the cleanup part
On top of this patch...

Regards,
Kedar.

> 
> --
> ~Vinod

Re: [PATCH v12 1/2] Documentation: DT: dma: Add Xilinx zynqmp dma device tree binding documentation

[Vinod Koul]

On Fri, Jul 01, 2016 at 05:07:05PM +0530, Kedareswara rao Appana wrote:
> Device-tree binding documentation for Xilinx zynqmp dma engine
> used in Zynq UltraScale+ MPSoC.

And I missed the cleanup part, so both applied  now

-- 
~Vinod

Re: [PATCH v12 1/2] Documentation: DT: dma: Add Xilinx zynqmp dma device tree binding documentation

[Vinod Koul]

On Fri, Jul 01, 2016 at 05:07:05PM +0530, Kedareswara rao Appana wrote:
> Device-tree binding documentation for Xilinx zynqmp dma engine
> used in Zynq UltraScale+ MPSoC.

And I missed the cleanup part, so both applied  now

-- 
~Vinod

[PATCH v12 1/2] Documentation: DT: dma: Add Xilinx zynqmp dma device tree binding documentation

[Kedareswara rao Appana]

Device-tree binding documentation for Xilinx zynqmp dma engine
used in Zynq UltraScale+ MPSoC.

Acked-by: Rob Herring 
Signed-off-by: Punnaiah Choudary Kalluri 
Signed-off-by: Kedareswara rao Appana 
---
Changes in v12:
- None.
Changes in v11:
- None.
Changes in v10:
- Added Rob Acked-by in the commit message.
Changs in v9:
- Removed include sg runtime configuration parameter
  from the binding doc as suggested by Lars.
Changes in v8:
- Removed all the software runtime configuration parameters
  from the binding doc as suggested by the Lars.
Changes in v7:
- None.
Changes in v6:
- Removed desc-axi-cache/dst-axi-cache/src-axi-cache properties
  from the binding doc as it allow broken combinations when dma-coherent
  is set as suggested by Rob.
- Fixed minor comments given by Rob related coding(lower case DT node name).
Changes in v5:
- Use dma-coherent flag for coherent transfers as suggested by rob.
- Removed unnecessary properties from binding doc as suggested by Rob.
Changes in v4:
- None
Changes in v3:
- None
Changes in v2:
- None.

 .../devicetree/bindings/dma/xilinx/zynqmp_dma.txt  |   27 
 1 files changed, 27 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt

diff --git a/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt 
b/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt
new file mode 100644
index 000..a784cdd
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt
@@ -0,0 +1,27 @@
+Xilinx ZynqMP DMA engine, it does support memory to memory transfers,
+memory to device and device to memory transfers. It also has flow
+control and rate control support for slave/peripheral dma access.
+
+Required properties:
+- compatible   : Should be "xlnx,zynqmp-dma-1.0"
+- reg  : Memory map for gdma/adma module access.
+- interrupt-parent : Interrupt controller the interrupt is routed through
+- interrupts   : Should contain DMA channel interrupt.
+- xlnx,bus-width   : Axi buswidth in bits. Should contain 128 or 64
+- clock-names  : List of input clocks "clk_main", "clk_apb"
+ (see clock bindings for details)
+
+Optional properties:
+- dma-coherent : Present if dma operations are coherent.
+
+Example:
+
+fpd_dma_chan1: dma@fd50 {
+   compatible = "xlnx,zynqmp-dma-1.0";
+   reg = <0x0 0xFD50 0x1000>;
+   interrupt-parent = <>;
+   interrupts = <0 117 4>;
+   clock-names = "clk_main", "clk_apb";
+   xlnx,bus-width = <128>;
+   dma-coherent;
+};
-- 
1.7.1

[PATCH v12 1/2] Documentation: DT: dma: Add Xilinx zynqmp dma device tree binding documentation

[Kedareswara rao Appana]

Device-tree binding documentation for Xilinx zynqmp dma engine
used in Zynq UltraScale+ MPSoC.

Acked-by: Rob Herring 
Signed-off-by: Punnaiah Choudary Kalluri 
Signed-off-by: Kedareswara rao Appana 
---
Changes in v12:
- None.
Changes in v11:
- None.
Changes in v10:
- Added Rob Acked-by in the commit message.
Changs in v9:
- Removed include sg runtime configuration parameter
  from the binding doc as suggested by Lars.
Changes in v8:
- Removed all the software runtime configuration parameters
  from the binding doc as suggested by the Lars.
Changes in v7:
- None.
Changes in v6:
- Removed desc-axi-cache/dst-axi-cache/src-axi-cache properties
  from the binding doc as it allow broken combinations when dma-coherent
  is set as suggested by Rob.
- Fixed minor comments given by Rob related coding(lower case DT node name).
Changes in v5:
- Use dma-coherent flag for coherent transfers as suggested by rob.
- Removed unnecessary properties from binding doc as suggested by Rob.
Changes in v4:
- None
Changes in v3:
- None
Changes in v2:
- None.

 .../devicetree/bindings/dma/xilinx/zynqmp_dma.txt  |   27 
 1 files changed, 27 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt

diff --git a/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt 
b/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt
new file mode 100644
index 000..a784cdd
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt
@@ -0,0 +1,27 @@
+Xilinx ZynqMP DMA engine, it does support memory to memory transfers,
+memory to device and device to memory transfers. It also has flow
+control and rate control support for slave/peripheral dma access.
+
+Required properties:
+- compatible   : Should be "xlnx,zynqmp-dma-1.0"
+- reg  : Memory map for gdma/adma module access.
+- interrupt-parent : Interrupt controller the interrupt is routed through
+- interrupts   : Should contain DMA channel interrupt.
+- xlnx,bus-width   : Axi buswidth in bits. Should contain 128 or 64
+- clock-names  : List of input clocks "clk_main", "clk_apb"
+ (see clock bindings for details)
+
+Optional properties:
+- dma-coherent : Present if dma operations are coherent.
+
+Example:
+
+fpd_dma_chan1: dma@fd50 {
+   compatible = "xlnx,zynqmp-dma-1.0";
+   reg = <0x0 0xFD50 0x1000>;
+   interrupt-parent = <>;
+   interrupts = <0 117 4>;
+   clock-names = "clk_main", "clk_apb";
+   xlnx,bus-width = <128>;
+   dma-coherent;
+};
-- 
1.7.1