subject:"\[PATCH v12 2\/2\] dmaengine\: Add Xilinx zynqmp dma engine driver support"

RE: [PATCH v12 2/2] dmaengine: Add Xilinx zynqmp dma engine driver support

2016-07-09 Thread Appana Durga Kedareswara Rao

Hi Vinod,

Thanks for the review...

> > +
> > +   chan->is_dmacoherent =  of_property_read_bool(node, "dma-
> coherent");
> > +   zdev->chan = chan;
> > +   tasklet_init(>tasklet, zynqmp_dma_do_tasklet, (ulong)chan);
> 
> where is this killed?

This is killed in the zynqmp_dma_chan_remove() API.

> 
> > +   spin_lock_init(>lock);
> > +   INIT_LIST_HEAD(>active_list);
> > +   INIT_LIST_HEAD(>pending_list);
> > +   INIT_LIST_HEAD(>done_list);
> > +   INIT_LIST_HEAD(>free_list);
> > +   zynqmp_dma_init(chan);
> > +   chan->irq = platform_get_irq(pdev, 0);
> > +   if (chan->irq < 0)
> > +   return -ENXIO;
> > +   err = devm_request_irq(>dev, chan->irq,
> zynqmp_dma_irq_handler, 0,
> > +  "zynqmp-dma", chan);
> 
> this needs to be freed/diabled in remove, dont see that

It is freed in the zynqmp_dma_chan_remove() API.

Regards,
Kedar.

RE: [PATCH v12 2/2] dmaengine: Add Xilinx zynqmp dma engine driver support

2016-07-09 Thread Appana Durga Kedareswara Rao

Hi Vinod,

Thanks for the review...

> > +
> > +   chan->is_dmacoherent =  of_property_read_bool(node, "dma-
> coherent");
> > +   zdev->chan = chan;
> > +   tasklet_init(>tasklet, zynqmp_dma_do_tasklet, (ulong)chan);
> 
> where is this killed?

This is killed in the zynqmp_dma_chan_remove() API.

> 
> > +   spin_lock_init(>lock);
> > +   INIT_LIST_HEAD(>active_list);
> > +   INIT_LIST_HEAD(>pending_list);
> > +   INIT_LIST_HEAD(>done_list);
> > +   INIT_LIST_HEAD(>free_list);
> > +   zynqmp_dma_init(chan);
> > +   chan->irq = platform_get_irq(pdev, 0);
> > +   if (chan->irq < 0)
> > +   return -ENXIO;
> > +   err = devm_request_irq(>dev, chan->irq,
> zynqmp_dma_irq_handler, 0,
> > +  "zynqmp-dma", chan);
> 
> this needs to be freed/diabled in remove, dont see that

It is freed in the zynqmp_dma_chan_remove() API.

Regards,
Kedar.

Re: [PATCH v12 2/2] dmaengine: Add Xilinx zynqmp dma engine driver support

2016-07-07 Thread Vinod Koul

On Fri, Jul 01, 2016 at 05:07:06PM +0530, Kedareswara rao Appana wrote:
> +static int zynqmp_dma_chan_probe(struct zynqmp_dma_device *zdev,
> +struct platform_device *pdev)
> +{
> + struct zynqmp_dma_chan *chan;
> + struct resource *res;
> + struct device_node *node = pdev->dev.of_node;
> + int err;
> +
> + chan = devm_kzalloc(zdev->dev, sizeof(*chan), GFP_KERNEL);
> + if (!chan)
> + return -ENOMEM;
> + chan->dev = zdev->dev;
> + chan->zdev = zdev;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + chan->regs = devm_ioremap_resource(>dev, res);
> + if (IS_ERR(chan->regs))
> + return PTR_ERR(chan->regs);
> +
> + chan->bus_width = ZYNQMP_DMA_BUS_WIDTH_64;
> + chan->dst_burst_len = ZYNQMP_DMA_AWLEN_RST_VAL;
> + chan->src_burst_len = ZYNQMP_DMA_ARLEN_RST_VAL;
> + err = of_property_read_u32(node, "xlnx,bus-width", >bus_width);
> + if ((err < 0) && ((chan->bus_width != ZYNQMP_DMA_BUS_WIDTH_64) ||
> +   (chan->bus_width != ZYNQMP_DMA_BUS_WIDTH_128))) {
> + dev_err(zdev->dev, "invalid bus-width value");
> + return err;
> + }
> +
> + chan->is_dmacoherent =  of_property_read_bool(node, "dma-coherent");
> + zdev->chan = chan;
> + tasklet_init(>tasklet, zynqmp_dma_do_tasklet, (ulong)chan);

where is this killed?

> + spin_lock_init(>lock);
> + INIT_LIST_HEAD(>active_list);
> + INIT_LIST_HEAD(>pending_list);
> + INIT_LIST_HEAD(>done_list);
> + INIT_LIST_HEAD(>free_list);
> +
> + dma_cookie_init(>common);
> + chan->common.device = >common;
> + list_add_tail(>common.device_node, >common.channels);
> +
> + zynqmp_dma_init(chan);
> + chan->irq = platform_get_irq(pdev, 0);
> + if (chan->irq < 0)
> + return -ENXIO;
> + err = devm_request_irq(>dev, chan->irq, zynqmp_dma_irq_handler, 0,
> +"zynqmp-dma", chan);

this needs to be freed/diabled in remove, dont see that

-- 
~Vinod

Re: [PATCH v12 2/2] dmaengine: Add Xilinx zynqmp dma engine driver support

2016-07-07 Thread Vinod Koul

On Fri, Jul 01, 2016 at 05:07:06PM +0530, Kedareswara rao Appana wrote:
> +static int zynqmp_dma_chan_probe(struct zynqmp_dma_device *zdev,
> +struct platform_device *pdev)
> +{
> + struct zynqmp_dma_chan *chan;
> + struct resource *res;
> + struct device_node *node = pdev->dev.of_node;
> + int err;
> +
> + chan = devm_kzalloc(zdev->dev, sizeof(*chan), GFP_KERNEL);
> + if (!chan)
> + return -ENOMEM;
> + chan->dev = zdev->dev;
> + chan->zdev = zdev;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + chan->regs = devm_ioremap_resource(>dev, res);
> + if (IS_ERR(chan->regs))
> + return PTR_ERR(chan->regs);
> +
> + chan->bus_width = ZYNQMP_DMA_BUS_WIDTH_64;
> + chan->dst_burst_len = ZYNQMP_DMA_AWLEN_RST_VAL;
> + chan->src_burst_len = ZYNQMP_DMA_ARLEN_RST_VAL;
> + err = of_property_read_u32(node, "xlnx,bus-width", >bus_width);
> + if ((err < 0) && ((chan->bus_width != ZYNQMP_DMA_BUS_WIDTH_64) ||
> +   (chan->bus_width != ZYNQMP_DMA_BUS_WIDTH_128))) {
> + dev_err(zdev->dev, "invalid bus-width value");
> + return err;
> + }
> +
> + chan->is_dmacoherent =  of_property_read_bool(node, "dma-coherent");
> + zdev->chan = chan;
> + tasklet_init(>tasklet, zynqmp_dma_do_tasklet, (ulong)chan);

where is this killed?

> + spin_lock_init(>lock);
> + INIT_LIST_HEAD(>active_list);
> + INIT_LIST_HEAD(>pending_list);
> + INIT_LIST_HEAD(>done_list);
> + INIT_LIST_HEAD(>free_list);
> +
> + dma_cookie_init(>common);
> + chan->common.device = >common;
> + list_add_tail(>common.device_node, >common.channels);
> +
> + zynqmp_dma_init(chan);
> + chan->irq = platform_get_irq(pdev, 0);
> + if (chan->irq < 0)
> + return -ENXIO;
> + err = devm_request_irq(>dev, chan->irq, zynqmp_dma_irq_handler, 0,
> +"zynqmp-dma", chan);

this needs to be freed/diabled in remove, dont see that

-- 
~Vinod

[PATCH v12 2/2] dmaengine: Add Xilinx zynqmp dma engine driver support

2016-07-01 Thread Kedareswara rao Appana

Added the driver for zynqmp dma engine used in Zynq
UltraScale+ MPSoC. This dma controller supports memory to memory
and I/O to I/O buffer transfers.

Signed-off-by: Kedareswara rao Appana 
---
Changes for v12:
- Removed zynqmp_dma_config structure as suggested by vinod.
- For slave usages using the dma_slave_config as suggsted by vinod.
Changes for v11:
- Fixed Kconfig/Make file order as suggested by Vinod.
- Removed unnecessary head files
- Fixed coding style comments line spaces etc...as suggested by vinod.
- Used dma_cookie_status as status call back.
- Used EXPORT_SYMBOL_GPL instead of EXPORT_SYMBOL as suggested by vinod.
Changes for v10:
- Use 64bit write for 64-bit platforms as suggested by Shubhrajyoti.
Changes for v9:
- Derive the include sg software runtime configuration parameter
  through config strucutre as suggested by the Lars.
Changes for v8:
- Derive the software runtime configuration parameters
  through config strucutre and configure them during transfer
  as suggested by the Lars.
Changes for v7:
- Fixed kbuild compilation warnings.
- Fixed {src,dst}_addr_widths are supposed to be a bitmask of
  supported slave device widths as suggested by Rob.
Changes in v6:
- Removed unnecessary axcache properties from the driver
- Fixed compilation issues
Changes in v5:
- Removed in_interrupt check from the tasklet cleanup as
  suggested by the vinod/lars.
Changes in v4:
- Modified the defines to start with ZYNQMP_DMA perfix
- Changed the zynqmp_dma_alloc_chan_resources to return number of
  allocated descriptors
- Changed the zynqmp_dma_device variable name
- Released the locks before calling user callback
- freeup irq in zynqmp_dma_chan_remove function.
Changes in v3:
- Modified the zynqmp_dma_chan_is_idle function return type to bool
Changes in v2:
- Corrected the function header documentation
- Framework expects bus-width value in bytes. so, fixed it
- Removed magic numbers for bus-width

 drivers/dma/Kconfig |7 +
 drivers/dma/xilinx/Makefile |1 +
 drivers/dma/xilinx/zynqmp_dma.c | 1145 +++
 3 files changed, 1153 insertions(+), 0 deletions(-)
 create mode 100644 drivers/dma/xilinx/zynqmp_dma.c

diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index 8c98779..01a53ed 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -533,6 +533,13 @@ config XILINX_VDMA
  channels, Memory Mapped to Stream (MM2S) and Stream to
  Memory Mapped (S2MM) for the data transfers.
 
+config XILINX_ZYNQMP_DMA
+   tristate "Xilinx ZynqMP DMA Engine"
+   depends on (ARCH_ZYNQ || MICROBLAZE || ARM64)
+   select DMA_ENGINE
+   help
+ Enable support for Xilinx ZynqMP DMA controller.
+
 config ZX_DMA
tristate "ZTE ZX296702 DMA support"
depends on ARCH_ZX
diff --git a/drivers/dma/xilinx/Makefile b/drivers/dma/xilinx/Makefile
index 3c4e9f2..95469dc 100644
--- a/drivers/dma/xilinx/Makefile
+++ b/drivers/dma/xilinx/Makefile
@@ -1 +1,2 @@
 obj-$(CONFIG_XILINX_VDMA) += xilinx_vdma.o
+obj-$(CONFIG_XILINX_ZYNQMP_DMA) += zynqmp_dma.o
diff --git a/drivers/dma/xilinx/zynqmp_dma.c b/drivers/dma/xilinx/zynqmp_dma.c
new file mode 100644
index 000..66020ff
--- /dev/null
+++ b/drivers/dma/xilinx/zynqmp_dma.c
@@ -0,0 +1,1145 @@
+/*
+ * DMA driver for Xilinx ZynqMP DMA Engine
+ *
+ * Copyright (C) 2016 Xilinx, Inc. All rights reserved.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "../dmaengine.h"
+
+/* Register Offsets */
+#define ZYNQMP_DMA_ISR 0x100
+#define ZYNQMP_DMA_IMR 0x104
+#define ZYNQMP_DMA_IER 0x108
+#define ZYNQMP_DMA_IDS 0x10C
+#define ZYNQMP_DMA_CTRL0   0x110
+#define ZYNQMP_DMA_CTRL1   0x114
+#define ZYNQMP_DMA_DATA_ATTR   0x120
+#define ZYNQMP_DMA_DSCR_ATTR   0x124
+#define ZYNQMP_DMA_SRC_DSCR_WRD0   0x128
+#define ZYNQMP_DMA_SRC_DSCR_WRD1   0x12C
+#define ZYNQMP_DMA_SRC_DSCR_WRD2   0x130
+#define ZYNQMP_DMA_SRC_DSCR_WRD3   0x134
+#define ZYNQMP_DMA_DST_DSCR_WRD0   0x138
+#define ZYNQMP_DMA_DST_DSCR_WRD1   0x13C
+#define ZYNQMP_DMA_DST_DSCR_WRD2   0x140
+#define ZYNQMP_DMA_DST_DSCR_WRD3   0x144
+#define ZYNQMP_DMA_SRC_START_LSB   0x158
+#define ZYNQMP_DMA_SRC_START_MSB   0x15C
+#define ZYNQMP_DMA_DST_START_LSB   0x160
+#define ZYNQMP_DMA_DST_START_MSB   0x164
+#define ZYNQMP_DMA_RATE_CTRL   0x18C
+#define ZYNQMP_DMA_IRQ_SRC_ACCT0x190
+#define ZYNQMP_DMA_IRQ_DST_ACCT0x194
+#define ZYNQMP_DMA_CTRL2

[PATCH v12 2/2] dmaengine: Add Xilinx zynqmp dma engine driver support

2016-07-01 Thread Kedareswara rao Appana

Added the driver for zynqmp dma engine used in Zynq
UltraScale+ MPSoC. This dma controller supports memory to memory
and I/O to I/O buffer transfers.

Signed-off-by: Kedareswara rao Appana 
---
Changes for v12:
- Removed zynqmp_dma_config structure as suggested by vinod.
- For slave usages using the dma_slave_config as suggsted by vinod.
Changes for v11:
- Fixed Kconfig/Make file order as suggested by Vinod.
- Removed unnecessary head files
- Fixed coding style comments line spaces etc...as suggested by vinod.
- Used dma_cookie_status as status call back.
- Used EXPORT_SYMBOL_GPL instead of EXPORT_SYMBOL as suggested by vinod.
Changes for v10:
- Use 64bit write for 64-bit platforms as suggested by Shubhrajyoti.
Changes for v9:
- Derive the include sg software runtime configuration parameter
  through config strucutre as suggested by the Lars.
Changes for v8:
- Derive the software runtime configuration parameters
  through config strucutre and configure them during transfer
  as suggested by the Lars.
Changes for v7:
- Fixed kbuild compilation warnings.
- Fixed {src,dst}_addr_widths are supposed to be a bitmask of
  supported slave device widths as suggested by Rob.
Changes in v6:
- Removed unnecessary axcache properties from the driver
- Fixed compilation issues
Changes in v5:
- Removed in_interrupt check from the tasklet cleanup as
  suggested by the vinod/lars.
Changes in v4:
- Modified the defines to start with ZYNQMP_DMA perfix
- Changed the zynqmp_dma_alloc_chan_resources to return number of
  allocated descriptors
- Changed the zynqmp_dma_device variable name
- Released the locks before calling user callback
- freeup irq in zynqmp_dma_chan_remove function.
Changes in v3:
- Modified the zynqmp_dma_chan_is_idle function return type to bool
Changes in v2:
- Corrected the function header documentation
- Framework expects bus-width value in bytes. so, fixed it
- Removed magic numbers for bus-width

 drivers/dma/Kconfig |7 +
 drivers/dma/xilinx/Makefile |1 +
 drivers/dma/xilinx/zynqmp_dma.c | 1145 +++
 3 files changed, 1153 insertions(+), 0 deletions(-)
 create mode 100644 drivers/dma/xilinx/zynqmp_dma.c

diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index 8c98779..01a53ed 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -533,6 +533,13 @@ config XILINX_VDMA
  channels, Memory Mapped to Stream (MM2S) and Stream to
  Memory Mapped (S2MM) for the data transfers.
 
+config XILINX_ZYNQMP_DMA
+   tristate "Xilinx ZynqMP DMA Engine"
+   depends on (ARCH_ZYNQ || MICROBLAZE || ARM64)
+   select DMA_ENGINE
+   help
+ Enable support for Xilinx ZynqMP DMA controller.
+
 config ZX_DMA
tristate "ZTE ZX296702 DMA support"
depends on ARCH_ZX
diff --git a/drivers/dma/xilinx/Makefile b/drivers/dma/xilinx/Makefile
index 3c4e9f2..95469dc 100644
--- a/drivers/dma/xilinx/Makefile
+++ b/drivers/dma/xilinx/Makefile
@@ -1 +1,2 @@
 obj-$(CONFIG_XILINX_VDMA) += xilinx_vdma.o
+obj-$(CONFIG_XILINX_ZYNQMP_DMA) += zynqmp_dma.o
diff --git a/drivers/dma/xilinx/zynqmp_dma.c b/drivers/dma/xilinx/zynqmp_dma.c
new file mode 100644
index 000..66020ff
--- /dev/null
+++ b/drivers/dma/xilinx/zynqmp_dma.c
@@ -0,0 +1,1145 @@
+/*
+ * DMA driver for Xilinx ZynqMP DMA Engine
+ *
+ * Copyright (C) 2016 Xilinx, Inc. All rights reserved.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "../dmaengine.h"
+
+/* Register Offsets */
+#define ZYNQMP_DMA_ISR 0x100
+#define ZYNQMP_DMA_IMR 0x104
+#define ZYNQMP_DMA_IER 0x108
+#define ZYNQMP_DMA_IDS 0x10C
+#define ZYNQMP_DMA_CTRL0   0x110
+#define ZYNQMP_DMA_CTRL1   0x114
+#define ZYNQMP_DMA_DATA_ATTR   0x120
+#define ZYNQMP_DMA_DSCR_ATTR   0x124
+#define ZYNQMP_DMA_SRC_DSCR_WRD0   0x128
+#define ZYNQMP_DMA_SRC_DSCR_WRD1   0x12C
+#define ZYNQMP_DMA_SRC_DSCR_WRD2   0x130
+#define ZYNQMP_DMA_SRC_DSCR_WRD3   0x134
+#define ZYNQMP_DMA_DST_DSCR_WRD0   0x138
+#define ZYNQMP_DMA_DST_DSCR_WRD1   0x13C
+#define ZYNQMP_DMA_DST_DSCR_WRD2   0x140
+#define ZYNQMP_DMA_DST_DSCR_WRD3   0x144
+#define ZYNQMP_DMA_SRC_START_LSB   0x158
+#define ZYNQMP_DMA_SRC_START_MSB   0x15C
+#define ZYNQMP_DMA_DST_START_LSB   0x160
+#define ZYNQMP_DMA_DST_START_MSB   0x164
+#define ZYNQMP_DMA_RATE_CTRL   0x18C
+#define ZYNQMP_DMA_IRQ_SRC_ACCT0x190
+#define ZYNQMP_DMA_IRQ_DST_ACCT0x194
+#define ZYNQMP_DMA_CTRL2   0x200
+
+/*

RE: [PATCH v12 2/2] dmaengine: Add Xilinx zynqmp dma engine driver support

RE: [PATCH v12 2/2] dmaengine: Add Xilinx zynqmp dma engine driver support

Re: [PATCH v12 2/2] dmaengine: Add Xilinx zynqmp dma engine driver support

Re: [PATCH v12 2/2] dmaengine: Add Xilinx zynqmp dma engine driver support

[PATCH v12 2/2] dmaengine: Add Xilinx zynqmp dma engine driver support

[PATCH v12 2/2] dmaengine: Add Xilinx zynqmp dma engine driver support

6 matches

Site Navigation

Mail list logo

Footer information