On Mon, Sep 29, 2014 at 08:20:30PM +0100, Al Stone wrote:
> On 09/29/2014 08:29 AM, Liviu Dudau wrote:
> > Some architectures do not have a simple view of the PCI I/O space and
> > instead use a range of CPU addresses that map to bus addresses. For some
> > architectures these ranges will be
On Mon, Sep 29, 2014 at 08:20:30PM +0100, Al Stone wrote:
On 09/29/2014 08:29 AM, Liviu Dudau wrote:
Some architectures do not have a simple view of the PCI I/O space and
instead use a range of CPU addresses that map to bus addresses. For some
architectures these ranges will be expressed
On 09/29/2014 08:29 AM, Liviu Dudau wrote:
> Some architectures do not have a simple view of the PCI I/O space and
> instead use a range of CPU addresses that map to bus addresses. For some
> architectures these ranges will be expressed by OF bindings in a device
> tree file.
>
> This patch
Some architectures do not have a simple view of the PCI I/O space and
instead use a range of CPU addresses that map to bus addresses. For some
architectures these ranges will be expressed by OF bindings in a device
tree file.
This patch introduces a pci_register_io_range() helper function with a
Some architectures do not have a simple view of the PCI I/O space and
instead use a range of CPU addresses that map to bus addresses. For some
architectures these ranges will be expressed by OF bindings in a device
tree file.
This patch introduces a pci_register_io_range() helper function with a
On 09/29/2014 08:29 AM, Liviu Dudau wrote:
Some architectures do not have a simple view of the PCI I/O space and
instead use a range of CPU addresses that map to bus addresses. For some
architectures these ranges will be expressed by OF bindings in a device
tree file.
This patch introduces
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