Hello,
Paul Cercueil wrote:
> The config0 register in the Xburst CPUs with a processor ID of
> PRID_COMP_INGENIC_D0 report themselves as MIPS32r2 compatible,
> but they don't actually support this ISA.
>
> Signed-off-by: Paul Cercueil
Applied to mips-next.
Thanks,
Paul
[ This message was
The config0 register in the Xburst CPUs with a processor ID of
PRID_COMP_INGENIC_D0 report themselves as MIPS32r2 compatible,
but they don't actually support this ISA.
Signed-off-by: Paul Cercueil
---
Notes:
v2: Apply fix according to the PRID
arch/mips/kernel/cpu-probe.c | 8
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