Re: [PATCH v2] riscv: force __cpu_up_ variables to put in data section
On Mon, 04 May 2020 10:37:40 PDT (-0700), ati...@atishpatra.org wrote: On Mon, May 4, 2020 at 12:50 AM Andreas Schwab wrote: On Mai 04 2020, Anup Patel wrote: > Slightly improved text: > > This issue happens on random booting of multiple harts, which means > it will manifest for BBL and OpenSBI v0.6 (or older version). In OpenSBI > v0.7 (or higher version), we have HSM extension so all the secondary harts > are brought-up by Linux kernel in an orderly fashion. This means we don't > this change for OpenSBI v0.7 (or higher version). +need Andreas. -- Andreas Schwab, sch...@linux-m68k.org GPG Key fingerprint = 7578 EB47 D4E5 4D69 2510 2552 DF73 E780 A9DA AEC1 "And now for something completely different." With Andreas & Anup's nitpick addressed, Reviewed-by: Atish Patra Thanks! It should be on fixes, with the new commit text.
Re: [PATCH v2] riscv: force __cpu_up_ variables to put in data section
On Mon, May 4, 2020 at 12:50 AM Andreas Schwab wrote: > > On Mai 04 2020, Anup Patel wrote: > > > Slightly improved text: > > > > This issue happens on random booting of multiple harts, which means > > it will manifest for BBL and OpenSBI v0.6 (or older version). In OpenSBI > > v0.7 (or higher version), we have HSM extension so all the secondary harts > > are brought-up by Linux kernel in an orderly fashion. This means we don't > > this change for OpenSBI v0.7 (or higher version). > > +need > > Andreas. > > -- > Andreas Schwab, sch...@linux-m68k.org > GPG Key fingerprint = 7578 EB47 D4E5 4D69 2510 2552 DF73 E780 A9DA AEC1 > "And now for something completely different." With Andreas & Anup's nitpick addressed, Reviewed-by: Atish Patra -- Regards, Atish
Re: [PATCH v2] riscv: force __cpu_up_ variables to put in data section
On Mai 04 2020, Anup Patel wrote: > Slightly improved text: > > This issue happens on random booting of multiple harts, which means > it will manifest for BBL and OpenSBI v0.6 (or older version). In OpenSBI > v0.7 (or higher version), we have HSM extension so all the secondary harts > are brought-up by Linux kernel in an orderly fashion. This means we don't > this change for OpenSBI v0.7 (or higher version). +need Andreas. -- Andreas Schwab, sch...@linux-m68k.org GPG Key fingerprint = 7578 EB47 D4E5 4D69 2510 2552 DF73 E780 A9DA AEC1 "And now for something completely different."
Re: [PATCH v2] riscv: force __cpu_up_ variables to put in data section
On Mon, May 4, 2020 at 9:24 AM Zong Li wrote: > > Put __cpu_up_stack_pointer and __cpu_up_task_pointer in data section. > Currently, these two variables are put in bss section, there is a > potential risk that secondary harts get the uninitialized value before > main hart finishing the bss clearing. In this case, all secondary > harts would pass the waiting loop and enable the MMU before main hart > set up the page table. > > This issue happened on random booting of multiple harts, which means > it will manifest for BBL and OpenSBI which older than v0.6. In OpenSBI > v0.7, it had included HSM extension, all the secondary harts are > waiting in firmware, so it could work fine without this change. Slightly improved text: This issue happens on random booting of multiple harts, which means it will manifest for BBL and OpenSBI v0.6 (or older version). In OpenSBI v0.7 (or higher version), we have HSM extension so all the secondary harts are brought-up by Linux kernel in an orderly fashion. This means we don't this change for OpenSBI v0.7 (or higher version). > > Changes in v2: > - Add commit description about random booting. > > Signed-off-by: Zong Li > Reviewed-by: Greentime Hu > --- > arch/riscv/kernel/cpu_ops.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/riscv/kernel/cpu_ops.c b/arch/riscv/kernel/cpu_ops.c > index c4c33bf02369..0ec22354018c 100644 > --- a/arch/riscv/kernel/cpu_ops.c > +++ b/arch/riscv/kernel/cpu_ops.c > @@ -15,8 +15,8 @@ > > const struct cpu_operations *cpu_ops[NR_CPUS] __ro_after_init; > > -void *__cpu_up_stack_pointer[NR_CPUS]; > -void *__cpu_up_task_pointer[NR_CPUS]; > +void *__cpu_up_stack_pointer[NR_CPUS] __section(.data); > +void *__cpu_up_task_pointer[NR_CPUS] __section(.data); > > extern const struct cpu_operations cpu_ops_sbi; > extern const struct cpu_operations cpu_ops_spinwait; > -- > 2.26.1 > Apart from above, looks good to me. Reviewed-by: Anup Patel Regards, Anup
[PATCH v2] riscv: force __cpu_up_ variables to put in data section
Put __cpu_up_stack_pointer and __cpu_up_task_pointer in data section. Currently, these two variables are put in bss section, there is a potential risk that secondary harts get the uninitialized value before main hart finishing the bss clearing. In this case, all secondary harts would pass the waiting loop and enable the MMU before main hart set up the page table. This issue happened on random booting of multiple harts, which means it will manifest for BBL and OpenSBI which older than v0.6. In OpenSBI v0.7, it had included HSM extension, all the secondary harts are waiting in firmware, so it could work fine without this change. Changes in v2: - Add commit description about random booting. Signed-off-by: Zong Li Reviewed-by: Greentime Hu --- arch/riscv/kernel/cpu_ops.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/riscv/kernel/cpu_ops.c b/arch/riscv/kernel/cpu_ops.c index c4c33bf02369..0ec22354018c 100644 --- a/arch/riscv/kernel/cpu_ops.c +++ b/arch/riscv/kernel/cpu_ops.c @@ -15,8 +15,8 @@ const struct cpu_operations *cpu_ops[NR_CPUS] __ro_after_init; -void *__cpu_up_stack_pointer[NR_CPUS]; -void *__cpu_up_task_pointer[NR_CPUS]; +void *__cpu_up_stack_pointer[NR_CPUS] __section(.data); +void *__cpu_up_task_pointer[NR_CPUS] __section(.data); extern const struct cpu_operations cpu_ops_sbi; extern const struct cpu_operations cpu_ops_spinwait; -- 2.26.1
