On 9/26/2012 11:40 PM, Murali Karicheri wrote:
> +struct clk_davinci_pll_data {
> + /* physical addresses set by platform code */
> + u32 phy_pllm;
> + /* if PLL has a prediv register this should be non zero */
> + u32 phy_prediv;
> + /* if PLL has a postdiv register this
On 9/26/2012 11:40 PM, Murali Karicheri wrote:
+struct clk_davinci_pll_data {
+ /* physical addresses set by platform code */
+ u32 phy_pllm;
+ /* if PLL has a prediv register this should be non zero */
+ u32 phy_prediv;
+ /* if PLL has a postdiv register this should be
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