Prefer using the BIT macro to define bit fileds
Cc: Florian Fainelli
Signed-off-by: Chunfeng Yun
---
v2: add Cc Florian
---
drivers/usb/gadget/udc/bdc/bdc.h | 84
1 file changed, 42 insertions(+), 42 deletions(-)
diff --git a/drivers/usb/gadget/udc/bdc/bdc.h b/drivers/usb/gadget/udc/bdc/bdc.h
index f8d5958..8d00b12 100644
--- a/drivers/usb/gadget/udc/bdc/bdc.h
+++ b/drivers/usb/gadget/udc/bdc/bdc.h
@@ -102,7 +102,7 @@
#define BDC_SPB(p) ((p) & 0x7)
/* BDC Capability1 */
-#define BDC_P64(1 << 0)
+#define BDC_P64BIT(0)
/* BDC Command register */
#define BDC_CMD_FH 0xe
@@ -111,7 +111,7 @@
#define BDC_CMD_BLA0x3
#define BDC_CMD_EPC0x2
#define BDC_CMD_DVC0x1
-#define BDC_CMD_CWS(0x1 << 5)
+#define BDC_CMD_CWSBIT(5)
#define BDC_CMD_CST(p) (((p) & (0xf << 6))>>6)
#define BDC_CMD_EPN(p) (((p) & 0x1f) << 10)
#define BDC_SUB_CMD_ADD(0x1 << 17)
@@ -124,7 +124,7 @@
#define BDC_SUB_CMD_EP_STP (0x2 << 17)
#define BDC_SUB_CMD_EP_STL (0x4 << 17)
#define BDC_SUB_CMD_EP_RST (0x1 << 17)
-#define BDC_CMD_SRD(1 << 27)
+#define BDC_CMD_SRDBIT(27)
/* CMD completion status */
#define BDC_CMDS_SUCC 0x1
@@ -141,19 +141,19 @@
#define EPM_SHIFT 4
/* BDC USPSC */
-#define BDC_VBC(1 << 31)
-#define BDC_PRC(1 << 30)
-#define BDC_PCE(1 << 29)
-#define BDC_CFC(1 << 28)
-#define BDC_PCC(1 << 27)
-#define BDC_PSC(1 << 26)
-#define BDC_VBS(1 << 25)
-#define BDC_PRS(1 << 24)
-#define BDC_PCS(1 << 23)
+#define BDC_VBCBIT(31)
+#define BDC_PRCBIT(30)
+#define BDC_PCEBIT(29)
+#define BDC_CFCBIT(28)
+#define BDC_PCCBIT(27)
+#define BDC_PSCBIT(26)
+#define BDC_VBSBIT(25)
+#define BDC_PRSBIT(24)
+#define BDC_PCSBIT(23)
#define BDC_PSP(p) (((p) & (0x7 << 20))>>20)
-#define BDC_SCN(1 << 8)
-#define BDC_SDC(1 << 7)
-#define BDC_SWS(1 << 4)
+#define BDC_SCNBIT(8)
+#define BDC_SDCBIT(7)
+#define BDC_SWSBIT(4)
#define BDC_USPSC_RW (BDC_SCN|BDC_SDC|BDC_SWS|0xf)
#define BDC_PSP(p) (((p) & (0x7 << 20))>>20)
@@ -167,17 +167,17 @@
#define BDC_PST_MASK 0xf
/* USPPMS */
-#define BDC_U2E(0x1 << 31)
-#define BDC_U1E(0x1 << 30)
-#define BDC_U2A(0x1 << 29)
-#define BDC_PORT_W1S (0x1 << 17)
+#define BDC_U2EBIT(31)
+#define BDC_U1EBIT(30)
+#define BDC_U2ABIT(29)
+#define BDC_PORT_W1S BIT(17)
#define BDC_U1T(p) ((p) & 0xff)
#define BDC_U2T(p) (((p) & 0xff) << 8)
#define BDC_U1T_MASK 0xff
/* USBPM2 */
/* Hardware LPM Enable */
-#define BDC_HLE(1 << 16)
+#define BDC_HLEBIT(16)
/* BDC Status and Control */
#define BDC_COP_RST(1 << 29)
@@ -186,11 +186,11 @@
#define BDC_COP_MASK (BDC_COP_RST|BDC_COP_RUN|BDC_COP_STP)
-#define BDC_COS(1 << 28)
+#define BDC_COSBIT(28)
#define BDC_CSTS(p)(((p) & (0x7 << 20)) >> 20)
-#define BDC_MASK_MCW (1 << 7)
-#define BDC_GIE(1 << 1)
-#define BDC_GIP(1 << 0)
+#define BDC_MASK_MCW BIT(7)
+#define BDC_GIEBIT(1)
+#define BDC_GIPBIT(0)
#define BDC_HLT1
#define BDC_NOR2
@@ -201,19 +201,19 @@
#define BD_CHAIN 0xf
#define BD_TFS_SHIFT 4
-#define BD_SOT (1 << 26)
-#define BD_EOT (1 << 27)
-#define BD_ISP (1 << 29)
-#define BD_IOC (1 << 30)
-#define BD_SBF (1 << 31)
+#define BD_SOT BIT(26)
+#define BD_EOT BIT(27)
+#define BD_ISP BIT(29)
+#define BD_IOC BIT(30)
+#define BD_SBF BIT(31)
#define BD_INTR_TARGET(p) (((p) & 0x1f) << 27)
-#define BDC_SRR_RWS(1 << 4)
-#define BDC_SRR_RST(1 << 3)
-#define BDC_SRR_ISR(1 << 2)
-#define BDC_SRR_IE (1 << 1)
-#define BDC_SRR_IP (1 << 0)
+#define BDC_SRR_RWSBIT(4)
+#define BDC_SRR_RSTBIT(3)
+#define BDC_SRR_ISRBIT(2)
+#define BDC_SRR_IE BIT(1)
+#define BDC_SRR_IP BIT(0)
#define BDC_SRR_EPI(p) (((p) & (0xff << 24)) >> 24)
#define BDC_SRR_DPI(p) (((p) & (0xff << 16)) >> 16)
#define BDC_SRR_DPI_MASK 0x00ff
@@ -221,7 +221,7 @@
#define MARK_CHAIN_BD (BD_CHAIN|BD_EOT|BD_SOT)
/* Control transfer BD specific fields */
-#define BD_DIR_IN (1 << 25)
+#define BD_DIR_IN BIT(25)
#define BDC_PTC_MASK 0xf000
@@ -241,13 +241,13 @@
/* Transfer BD fields */
