Hi Paul,
On Wed, 2018-09-26 at 22:18 +, Paul Burton wrote:
> Hi Yasha,
>
> On Wed, Sep 26, 2018 at 02:16:15PM +0300, Yasha Cherikovsky wrote:
> > MIPSR6 CPUs do not support unaligned load/store instructions
> > (LWL, LWR, SWL, SWR and LDL, LDR, SDL, SDR for 64bit).
> >
> > Currently the
Hi Paul,
On Wed, 2018-09-26 at 22:18 +, Paul Burton wrote:
> Hi Yasha,
>
> On Wed, Sep 26, 2018 at 02:16:15PM +0300, Yasha Cherikovsky wrote:
> > MIPSR6 CPUs do not support unaligned load/store instructions
> > (LWL, LWR, SWL, SWR and LDL, LDR, SDL, SDR for 64bit).
> >
> > Currently the
Hi Yasha,
On Wed, Sep 26, 2018 at 02:16:15PM +0300, Yasha Cherikovsky wrote:
> MIPSR6 CPUs do not support unaligned load/store instructions
> (LWL, LWR, SWL, SWR and LDL, LDR, SDL, SDR for 64bit).
>
> Currently the MIPS tree has some special cases to avoid these
> instructions, and the code is
Hi Yasha,
On Wed, Sep 26, 2018 at 02:16:15PM +0300, Yasha Cherikovsky wrote:
> MIPSR6 CPUs do not support unaligned load/store instructions
> (LWL, LWR, SWL, SWR and LDL, LDR, SDL, SDR for 64bit).
>
> Currently the MIPS tree has some special cases to avoid these
> instructions, and the code is
MIPSR6 CPUs do not support unaligned load/store instructions
(LWL, LWR, SWL, SWR and LDL, LDR, SDL, SDR for 64bit).
Currently the MIPS tree has some special cases to avoid these
instructions, and the code is testing for !CONFIG_CPU_MIPSR6.
This patch declares a new Kconfig variable:
MIPSR6 CPUs do not support unaligned load/store instructions
(LWL, LWR, SWL, SWR and LDL, LDR, SDL, SDR for 64bit).
Currently the MIPS tree has some special cases to avoid these
instructions, and the code is testing for !CONFIG_CPU_MIPSR6.
This patch declares a new Kconfig variable:
6 matches
Mail list logo