Re: [PATCH v2 1/2] dmaengine: avalon: Intel Avalon-MM DMA Interface for PCIe

2019-10-15 Thread Dan Carpenter
Ah that's fine then. And since wr_flags[hw->d2h_last_id] is just true/false then it doesn't matter if it races. regards, dan carpenter

Re: [PATCH v2 1/2] dmaengine: avalon: Intel Avalon-MM DMA Interface for PCIe

2019-10-15 Thread Alexander Gordeev
On Tue, Oct 15, 2019 at 04:19:55PM +0300, Dan Carpenter wrote: > On Tue, Oct 15, 2019 at 01:24:50PM +0200, Alexander Gordeev wrote: > > On Thu, Oct 10, 2019 at 02:30:34PM +0300, Dan Carpenter wrote: > > > On Thu, Oct 10, 2019 at 10:51:45AM +0200, Alexander Gordeev wrote: > > > > On Wed, Oct 09,

Re: [PATCH v2 1/2] dmaengine: avalon: Intel Avalon-MM DMA Interface for PCIe

2019-10-15 Thread Dan Carpenter
On Tue, Oct 15, 2019 at 01:24:50PM +0200, Alexander Gordeev wrote: > On Thu, Oct 10, 2019 at 02:30:34PM +0300, Dan Carpenter wrote: > > On Thu, Oct 10, 2019 at 10:51:45AM +0200, Alexander Gordeev wrote: > > > On Wed, Oct 09, 2019 at 09:53:23PM +0300, Dan Carpenter wrote: > > > > > > > + u32

Re: [PATCH v2 1/2] dmaengine: avalon: Intel Avalon-MM DMA Interface for PCIe

2019-10-15 Thread Alexander Gordeev
On Tue, Oct 15, 2019 at 04:03:21PM +0530, Vinod Koul wrote: > what kind of device is this? I dont think we want these and the ones > coming below as part of kernel kconfig! Yes, I have already been pointed out on this and will put those as kernel module parameters in the next version. The device

Re: [PATCH v2 1/2] dmaengine: avalon: Intel Avalon-MM DMA Interface for PCIe

2019-10-15 Thread Alexander Gordeev
On Tue, Oct 15, 2019 at 02:41:08PM +0300, Dan Carpenter wrote: > > > > > > > > + spin_lock(lock); > > > > [*] > > [ snip ] > > > I struggle to realize how the spinlock I use (see [*] above) does not > > protect the reader. > > Argh I'm really sorry. I completely didn't see the

Re: [PATCH v2 1/2] dmaengine: avalon: Intel Avalon-MM DMA Interface for PCIe

2019-10-15 Thread Dan Carpenter
On Tue, Oct 15, 2019 at 01:24:50PM +0200, Alexander Gordeev wrote: > On Thu, Oct 10, 2019 at 02:30:34PM +0300, Dan Carpenter wrote: > > On Thu, Oct 10, 2019 at 10:51:45AM +0200, Alexander Gordeev wrote: > > > On Wed, Oct 09, 2019 at 09:53:23PM +0300, Dan Carpenter wrote: > > > > > > > + u32

Re: [PATCH v2 1/2] dmaengine: avalon: Intel Avalon-MM DMA Interface for PCIe

2019-10-15 Thread Alexander Gordeev
On Thu, Oct 10, 2019 at 02:30:34PM +0300, Dan Carpenter wrote: > On Thu, Oct 10, 2019 at 10:51:45AM +0200, Alexander Gordeev wrote: > > On Wed, Oct 09, 2019 at 09:53:23PM +0300, Dan Carpenter wrote: > > > > > > + u32 *rd_flags = hw->dma_desc_table_rd.cpu_addr->flags; > > > > > > + u32

Re: [PATCH v2 1/2] dmaengine: avalon: Intel Avalon-MM DMA Interface for PCIe

2019-10-15 Thread Vinod Koul
On 09-10-19, 12:12, Alexander Gordeev wrote: > +config AVALON_DMA_CTRL_BASE > + hex "Avalon DMA controllers base" > + default "0x" what kind of device is this? I dont think we want these and the ones coming below as part of kernel kconfig! > +// SPDX-License-Identifier: GPL-2.0

Re: [PATCH v2 1/2] dmaengine: avalon: Intel Avalon-MM DMA Interface for PCIe

2019-10-10 Thread Dan Carpenter
On Thu, Oct 10, 2019 at 10:51:45AM +0200, Alexander Gordeev wrote: > On Wed, Oct 09, 2019 at 09:53:23PM +0300, Dan Carpenter wrote: > > > > > + u32 *rd_flags = hw->dma_desc_table_rd.cpu_addr->flags; > > > > > + u32 *wr_flags = hw->dma_desc_table_wr.cpu_addr->flags; > > > > > + struct

Re: [PATCH v2 1/2] dmaengine: avalon: Intel Avalon-MM DMA Interface for PCIe

2019-10-10 Thread Alexander Gordeev
On Wed, Oct 09, 2019 at 09:53:23PM +0300, Dan Carpenter wrote: > > > > + u32 *rd_flags = hw->dma_desc_table_rd.cpu_addr->flags; > > > > + u32 *wr_flags = hw->dma_desc_table_wr.cpu_addr->flags; > > > > + struct avalon_dma_desc *desc; > > > > + struct virt_dma_desc *vdesc; >

Re: [PATCH v2 1/2] dmaengine: avalon: Intel Avalon-MM DMA Interface for PCIe

2019-10-09 Thread Dan Carpenter
On Wed, Oct 09, 2019 at 04:58:12PM +0200, Alexander Gordeev wrote: > On Wed, Oct 09, 2019 at 03:14:41PM +0300, Dan Carpenter wrote: > > > +config AVALON_DMA_PCI_VENDOR_ID > > > + hex "PCI vendor ID" > > > + default "0x1172" > > > + > > > +config AVALON_DMA_PCI_DEVICE_ID > > > + hex "PCI device ID"

Re: [PATCH v2 1/2] dmaengine: avalon: Intel Avalon-MM DMA Interface for PCIe

2019-10-09 Thread Alexander Gordeev
On Wed, Oct 09, 2019 at 03:14:41PM +0300, Dan Carpenter wrote: > > +config AVALON_DMA_PCI_VENDOR_ID > > + hex "PCI vendor ID" > > + default "0x1172" > > + > > +config AVALON_DMA_PCI_DEVICE_ID > > + hex "PCI device ID" > > + default "0xe003" > > This feels wrong. Why isn't it known in

Re: [PATCH v2 1/2] dmaengine: avalon: Intel Avalon-MM DMA Interface for PCIe

2019-10-09 Thread Greg KH
On Wed, Oct 09, 2019 at 12:12:30PM +0200, Alexander Gordeev wrote: > +static int setup_dma_descs(struct dma_desc *dma_descs, > +struct avalon_dma_desc *desc) > +{ > + struct scatterlist *sg_stop; > + unsigned int sg_set; > + int ret; > + > + ret =

Re: [PATCH v2 1/2] dmaengine: avalon: Intel Avalon-MM DMA Interface for PCIe

2019-10-09 Thread Dan Carpenter
On Wed, Oct 09, 2019 at 12:12:30PM +0200, Alexander Gordeev wrote: > Support Avalon-MM DMA Interface for PCIe used in hard IPs for > Intel Arria, Cyclone or Stratix FPGAs. > > CC: Michael Chen > CC: de...@driverdev.osuosl.org > CC: dmaeng...@vger.kernel.org > > Signed-off-by: Alexander Gordeev

[PATCH v2 1/2] dmaengine: avalon: Intel Avalon-MM DMA Interface for PCIe

2019-10-09 Thread Alexander Gordeev
Support Avalon-MM DMA Interface for PCIe used in hard IPs for Intel Arria, Cyclone or Stratix FPGAs. CC: Michael Chen CC: de...@driverdev.osuosl.org CC: dmaeng...@vger.kernel.org Signed-off-by: Alexander Gordeev --- drivers/dma/Kconfig | 2 + drivers/dma/Makefile |