Re: [PATCH v2 1/3] dmaengine: add TI EDMA DMA engine driver
On Wed, Aug 22, 2012 at 12:37:18PM +, Hebbar, Gururaja wrote: > On Wed, Aug 22, 2012 at 00:13:07, Porter, Matt wrote: > > Add a DMA engine driver for the TI EDMA controller. This driver > > is implemented as a wrapper around the existing DaVinci private > > DMA implementation. This approach allows for incremental conversion > > of each peripheral driver to the DMA engine API. The EDMA driver > > supports slave transfers but does not yet support cyclic transfers. > > > > Signed-off-by: Matt Porter > > --- > > drivers/dma/Kconfig | 10 + > > drivers/dma/Makefile |1 + > > drivers/dma/edma.c | 684 > > ++ > > include/linux/edma.h | 29 +++ > > 4 files changed, 724 insertions(+) > > create mode 100644 drivers/dma/edma.c > > create mode 100644 include/linux/edma.h > > > > diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig > > index d06ea29..5064e85 100644 > > --- a/drivers/dma/Kconfig > > +++ b/drivers/dma/Kconfig > > @@ -208,6 +208,16 @@ config SIRF_DMA > > help > > Enable support for the CSR SiRFprimaII DMA engine. > > > > +config TI_EDMA > > + tristate "TI EDMA support" > > + depends on ARCH_DAVINCI > > + select DMA_ENGINE > > + select DMA_VIRTUAL_CHANNELS > > + default y > > + help > > + Enable support for the TI EDMA controller. This DMA > > + engine is found on TI DaVinci and AM33xx parts. > > + > > config ARCH_HAS_ASYNC_TX_FIND_CHANNEL > > bool > > > > diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile > > index 4cf6b12..f5cf310 100644 > > --- a/drivers/dma/Makefile > > +++ b/drivers/dma/Makefile > > @@ -23,6 +23,7 @@ obj-$(CONFIG_IMX_DMA) += imx-dma.o > > obj-$(CONFIG_MXS_DMA) += mxs-dma.o > > obj-$(CONFIG_TIMB_DMA) += timb_dma.o > > obj-$(CONFIG_SIRF_DMA) += sirf-dma.o > > +obj-$(CONFIG_TI_EDMA) += edma.o > > obj-$(CONFIG_STE_DMA40) += ste_dma40.o ste_dma40_ll.o > > obj-$(CONFIG_TEGRA20_APB_DMA) += tegra20-apb-dma.o > > obj-$(CONFIG_PL330_DMA) += pl330.o > > diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c > > new file mode 100644 > > index 000..bf15f81 > > --- /dev/null > > +++ b/drivers/dma/edma.c > > @@ -0,0 +1,684 @@ > > +/* > > + * TI EDMA DMA engine driver > > + * > > + * Copyright 2012 Texas Instruments > > + * > > + * This program is free software; you can redistribute it and/or > > + * modify it under the terms of the GNU General Public License as > > + * published by the Free Software Foundation version 2. > > + * > > + * This program is distributed "as is" WITHOUT ANY WARRANTY of any > > + * kind, whether express or implied; without even the implied warranty > > + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > > + * GNU General Public License for more details. > > + */ > > + > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > + > > +#include > > + > > +#include "dmaengine.h" > > +#include "virt-dma.h" > > + > > +/* > > + * This will go away when the private EDMA API is folded > > + * into this driver and the platform device(s) are > > + * instantiated in the arch code. We can only get away > > + * with this simplification because DA8XX may not be built > > + * in the same kernel image with other DaVinci parts. This > > + * avoids having to sprinkle dmaengine driver platform devices > > + * and data throughout all the existing board files. > > + */ > > +#ifdef CONFIG_ARCH_DAVINCI_DA8XX > > +#define EDMA_CTLRS 2 > > +#define EDMA_CHANS 32 > > +#else > > +#define EDMA_CTLRS 1 > > +#define EDMA_CHANS 64 > > +#endif /* CONFIG_ARCH_DAVINCI_DA8XX */ > > I believe you already have some modifications for your next version to handle > Different EDMA IP versions (AM335x). > They use/have cross-bar implementations as-well. I don't have those yet. That effort is a WIP atm. However, I should probably add more details to the approach I mentioned in the cover letter for this series. AM335x support will happen by migrating the private EDMA API to arm/common/. There's an incremental change to the private EDMA API implementation to handle AM335x's cross-bar support that exists right now only in the TI vendor tree. I'm going to add that, align the platform devices generated from hwmod data with the existing private EDMA driver expectations, and also add the DT bindings necessary to communicate all the hardware config that's currently carried in the mach-davinci/ board files. That will enable the private EDMA API on AM335x. What I have pushed so far to my WIP branch is: https://github.com/ohporter/linux/tree/WIP/edma-dmaengine-private-migration Completely non-functional on AM335x, but you can at least see where I'm going there. I'm working on the pdev/pdata/DT part mentioned above atm. In turn, since this driver is completely self-contained and sits only on top of the private EDMA API, it will then work on AM335x. This approach avoids having to
Re: [PATCH v2 1/3] dmaengine: add TI EDMA DMA engine driver
On Wed, Aug 22, 2012 at 09:09:26AM +0530, Vinod Koul wrote:
> On Tue, 2012-08-21 at 14:43 -0400, Matt Porter wrote:
> > Add a DMA engine driver for the TI EDMA controller. This driver
> > is implemented as a wrapper around the existing DaVinci private
> > DMA implementation. This approach allows for incremental conversion
> > of each peripheral driver to the DMA engine API. The EDMA driver
> > supports slave transfers but does not yet support cyclic transfers.
> >
> > Signed-off-by: Matt Porter
> mostly looks decent and in shape.
ok, thanks for the review. I'll be addressing these comments in v3.
Should happen before I go on holiday for the next week.
> > ---
> > +config TI_EDMA
> > + tristate "TI EDMA support"
> > + depends on ARCH_DAVINCI
> > + select DMA_ENGINE
> > + select DMA_VIRTUAL_CHANNELS
> > + default y
> default should be n for new drivers
ok
> > + help
> > + Enable support for the TI EDMA controller. This DMA
> > + engine is found on TI DaVinci and AM33xx parts.
> > +
> > config ARCH_HAS_ASYNC_TX_FIND_CHANNEL
> > bool
> >
> > +/* Max of 16 segments per channel to conserve PaRAM slots */
> > +#define MAX_NR_SG 16
> > +#define EDMA_MAX_SLOTS MAX_NR_SG
> > +#define EDMA_DESCRIPTORS 16
> > +
> > +struct edma_desc {
> > + struct virt_dma_descvdesc;
> > + struct list_headnode;
> > +
> dummy space?
will remove
> > + int absync;
> > + int pset_nr;
> > + struct edmacc_param pset[0];
> > +};
> > +
> > +struct edma_cc;
> > +
> > +struct edma_chan {
> > + struct virt_dma_chanvchan;
> > + struct list_headnode;
> > + struct edma_desc*edesc;
> > + struct edma_cc *ecc;
> > + int ch_num;
> > + boolalloced;
> > + int slot[EDMA_MAX_SLOTS];
> > +
> > + dma_addr_t addr;
> > + int addr_width;
> > + int maxburst;
> > +};
> > +
>
> > +/* Dispatch a queued descriptor to the controller (caller holds lock) */
> > +static void edma_execute(struct edma_chan *echan)
> > +{
> > + struct virt_dma_desc *vdesc = vchan_next_desc(>vchan);
> > + struct edma_desc *edesc;
> > + int i;
> > +
> > + if (!vdesc) {
> > + echan->edesc = NULL;
> > + return;
> > + }
> > +
> > + list_del(>node);
> > +
> > + echan->edesc = edesc = to_edma_desc(>tx);
> > +
> > + /* Write descriptor PaRAM set(s) */
> > + for (i = 0; i < edesc->pset_nr; i++) {
> > + edma_write_slot(echan->slot[i], >pset[i]);
> > + dev_dbg(echan->vchan.chan.device->dev,
> > + "\n pset[%d]:\n"
> > + " chnum\t%d\n"
> > + " slot\t%d\n"
> > + " opt\t%08x\n"
> > + " src\t%08x\n"
> > + " dst\t%08x\n"
> > + " abcnt\t%08x\n"
> > + " ccnt\t%08x\n"
> > + " bidx\t%08x\n"
> > + " cidx\t%08x\n"
> > + " lkrld\t%08x\n",
> > + i, echan->ch_num, echan->slot[i],
> > + edesc->pset[i].opt,
> > + edesc->pset[i].src,
> > + edesc->pset[i].dst,
> > + edesc->pset[i].a_b_cnt,
> > + edesc->pset[i].ccnt,
> > + edesc->pset[i].src_dst_bidx,
> > + edesc->pset[i].src_dst_cidx,
> > + edesc->pset[i].link_bcntrld);
> > + /* Link to the previous slot if not the last set */
> > + if (i != (edesc->pset_nr - 1))
> > + edma_link(echan->slot[i], echan->slot[i+1]);
> > + /* Final pset links to the dummy pset */
> > + else
> > + edma_link(echan->slot[i], echan->ecc->dummy_slot);
> > + }
> > +
> > + edma_start(echan->ch_num);
> > +}
> > +
> > +static int edma_terminate_all(struct edma_chan *echan)
> > +{
> > + unsigned long flags;
> > + LIST_HEAD(head);
> > +
> > + spin_lock_irqsave(>vchan.lock, flags);
> > +
> > + /*
> > +* Stop DMA activity: we assume the callback will not be called
> > +* after edma_dma() returns (even if it does, it will see
> > +* echan->edesc is NULL and exit.)
> > +*/
> > + if (echan->edesc) {
> > + echan->edesc = NULL;
> > + edma_stop(echan->ch_num);
> > + }
> > +
> > + vchan_get_all_descriptors(>vchan, );
> > + spin_unlock_irqrestore(>vchan.lock, flags);
> > + vchan_dma_desc_free_list(>vchan, );
> > +
> > + return 0;
> > +}
> > +
> > +
> > +static int edma_slave_config(struct edma_chan *echan,
> > + struct dma_slave_config *config)
> > +{
> > + if ((config->src_addr_width > DMA_SLAVE_BUSWIDTH_4_BYTES) ||
> > +
RE: [PATCH v2 1/3] dmaengine: add TI EDMA DMA engine driver
On Wed, Aug 22, 2012 at 00:13:07, Porter, Matt wrote:
> Add a DMA engine driver for the TI EDMA controller. This driver
> is implemented as a wrapper around the existing DaVinci private
> DMA implementation. This approach allows for incremental conversion
> of each peripheral driver to the DMA engine API. The EDMA driver
> supports slave transfers but does not yet support cyclic transfers.
>
> Signed-off-by: Matt Porter
> ---
> drivers/dma/Kconfig | 10 +
> drivers/dma/Makefile |1 +
> drivers/dma/edma.c | 684
> ++
> include/linux/edma.h | 29 +++
> 4 files changed, 724 insertions(+)
> create mode 100644 drivers/dma/edma.c
> create mode 100644 include/linux/edma.h
>
> diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
> index d06ea29..5064e85 100644
> --- a/drivers/dma/Kconfig
> +++ b/drivers/dma/Kconfig
> @@ -208,6 +208,16 @@ config SIRF_DMA
> help
> Enable support for the CSR SiRFprimaII DMA engine.
>
> +config TI_EDMA
> + tristate "TI EDMA support"
> + depends on ARCH_DAVINCI
> + select DMA_ENGINE
> + select DMA_VIRTUAL_CHANNELS
> + default y
> + help
> + Enable support for the TI EDMA controller. This DMA
> + engine is found on TI DaVinci and AM33xx parts.
> +
> config ARCH_HAS_ASYNC_TX_FIND_CHANNEL
> bool
>
> diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
> index 4cf6b12..f5cf310 100644
> --- a/drivers/dma/Makefile
> +++ b/drivers/dma/Makefile
> @@ -23,6 +23,7 @@ obj-$(CONFIG_IMX_DMA) += imx-dma.o
> obj-$(CONFIG_MXS_DMA) += mxs-dma.o
> obj-$(CONFIG_TIMB_DMA) += timb_dma.o
> obj-$(CONFIG_SIRF_DMA) += sirf-dma.o
> +obj-$(CONFIG_TI_EDMA) += edma.o
> obj-$(CONFIG_STE_DMA40) += ste_dma40.o ste_dma40_ll.o
> obj-$(CONFIG_TEGRA20_APB_DMA) += tegra20-apb-dma.o
> obj-$(CONFIG_PL330_DMA) += pl330.o
> diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c
> new file mode 100644
> index 000..bf15f81
> --- /dev/null
> +++ b/drivers/dma/edma.c
> @@ -0,0 +1,684 @@
> +/*
> + * TI EDMA DMA engine driver
> + *
> + * Copyright 2012 Texas Instruments
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation version 2.
> + *
> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
> + * kind, whether express or implied; without even the implied warranty
> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#include
> +
> +#include "dmaengine.h"
> +#include "virt-dma.h"
> +
> +/*
> + * This will go away when the private EDMA API is folded
> + * into this driver and the platform device(s) are
> + * instantiated in the arch code. We can only get away
> + * with this simplification because DA8XX may not be built
> + * in the same kernel image with other DaVinci parts. This
> + * avoids having to sprinkle dmaengine driver platform devices
> + * and data throughout all the existing board files.
> + */
> +#ifdef CONFIG_ARCH_DAVINCI_DA8XX
> +#define EDMA_CTLRS 2
> +#define EDMA_CHANS 32
> +#else
> +#define EDMA_CTLRS 1
> +#define EDMA_CHANS 64
> +#endif /* CONFIG_ARCH_DAVINCI_DA8XX */
I believe you already have some modifications for your next version to handle
Different EDMA IP versions (AM335x).
They use/have cross-bar implementations as-well.
> +
> +/* Max of 16 segments per channel to conserve PaRAM slots */
> +#define MAX_NR_SG16
> +#define EDMA_MAX_SLOTS MAX_NR_SG
Is it possible to get this (EDMA_MAX_SLOTS) from platform data?
> +#define EDMA_DESCRIPTORS 16
> +
> +struct edma_desc {
> + struct virt_dma_descvdesc;
> + struct list_headnode;
> +
> + int absync;
> + int pset_nr;
> + struct edmacc_param pset[0];
> +};
> +
> +struct edma_cc;
> +
> +struct edma_chan {
> + struct virt_dma_chanvchan;
> + struct list_headnode;
> + struct edma_desc*edesc;
> + struct edma_cc *ecc;
> + int ch_num;
> + boolalloced;
> + int slot[EDMA_MAX_SLOTS];
> +
> + dma_addr_t addr;
> + int addr_width;
> + int maxburst;
> +};
> +
> +struct edma_cc {
> + int ctlr;
> + struct dma_device dma_slave;
> + struct edma_chanslave_chans[EDMA_CHANS];
> + int num_slave_chans;
> + int dummy_slot;
> +};
> +
> +static
RE: [PATCH v2 1/3] dmaengine: add TI EDMA DMA engine driver
On Wed, Aug 22, 2012 at 00:13:07, Porter, Matt wrote:
Add a DMA engine driver for the TI EDMA controller. This driver
is implemented as a wrapper around the existing DaVinci private
DMA implementation. This approach allows for incremental conversion
of each peripheral driver to the DMA engine API. The EDMA driver
supports slave transfers but does not yet support cyclic transfers.
Signed-off-by: Matt Porter mpor...@ti.com
---
drivers/dma/Kconfig | 10 +
drivers/dma/Makefile |1 +
drivers/dma/edma.c | 684
++
include/linux/edma.h | 29 +++
4 files changed, 724 insertions(+)
create mode 100644 drivers/dma/edma.c
create mode 100644 include/linux/edma.h
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index d06ea29..5064e85 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -208,6 +208,16 @@ config SIRF_DMA
help
Enable support for the CSR SiRFprimaII DMA engine.
+config TI_EDMA
+ tristate TI EDMA support
+ depends on ARCH_DAVINCI
+ select DMA_ENGINE
+ select DMA_VIRTUAL_CHANNELS
+ default y
+ help
+ Enable support for the TI EDMA controller. This DMA
+ engine is found on TI DaVinci and AM33xx parts.
+
config ARCH_HAS_ASYNC_TX_FIND_CHANNEL
bool
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index 4cf6b12..f5cf310 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -23,6 +23,7 @@ obj-$(CONFIG_IMX_DMA) += imx-dma.o
obj-$(CONFIG_MXS_DMA) += mxs-dma.o
obj-$(CONFIG_TIMB_DMA) += timb_dma.o
obj-$(CONFIG_SIRF_DMA) += sirf-dma.o
+obj-$(CONFIG_TI_EDMA) += edma.o
obj-$(CONFIG_STE_DMA40) += ste_dma40.o ste_dma40_ll.o
obj-$(CONFIG_TEGRA20_APB_DMA) += tegra20-apb-dma.o
obj-$(CONFIG_PL330_DMA) += pl330.o
diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c
new file mode 100644
index 000..bf15f81
--- /dev/null
+++ b/drivers/dma/edma.c
@@ -0,0 +1,684 @@
+/*
+ * TI EDMA DMA engine driver
+ *
+ * Copyright 2012 Texas Instruments
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed as is WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include linux/dmaengine.h
+#include linux/dma-mapping.h
+#include linux/err.h
+#include linux/init.h
+#include linux/interrupt.h
+#include linux/list.h
+#include linux/module.h
+#include linux/platform_device.h
+#include linux/slab.h
+#include linux/spinlock.h
+
+#include mach/edma.h
+
+#include dmaengine.h
+#include virt-dma.h
+
+/*
+ * This will go away when the private EDMA API is folded
+ * into this driver and the platform device(s) are
+ * instantiated in the arch code. We can only get away
+ * with this simplification because DA8XX may not be built
+ * in the same kernel image with other DaVinci parts. This
+ * avoids having to sprinkle dmaengine driver platform devices
+ * and data throughout all the existing board files.
+ */
+#ifdef CONFIG_ARCH_DAVINCI_DA8XX
+#define EDMA_CTLRS 2
+#define EDMA_CHANS 32
+#else
+#define EDMA_CTLRS 1
+#define EDMA_CHANS 64
+#endif /* CONFIG_ARCH_DAVINCI_DA8XX */
I believe you already have some modifications for your next version to handle
Different EDMA IP versions (AM335x).
They use/have cross-bar implementations as-well.
+
+/* Max of 16 segments per channel to conserve PaRAM slots */
+#define MAX_NR_SG16
+#define EDMA_MAX_SLOTS MAX_NR_SG
Is it possible to get this (EDMA_MAX_SLOTS) from platform data?
+#define EDMA_DESCRIPTORS 16
+
+struct edma_desc {
+ struct virt_dma_descvdesc;
+ struct list_headnode;
+
+ int absync;
+ int pset_nr;
+ struct edmacc_param pset[0];
+};
+
+struct edma_cc;
+
+struct edma_chan {
+ struct virt_dma_chanvchan;
+ struct list_headnode;
+ struct edma_desc*edesc;
+ struct edma_cc *ecc;
+ int ch_num;
+ boolalloced;
+ int slot[EDMA_MAX_SLOTS];
+
+ dma_addr_t addr;
+ int addr_width;
+ int maxburst;
+};
+
+struct edma_cc {
+ int ctlr;
+ struct dma_device dma_slave;
+ struct edma_chanslave_chans[EDMA_CHANS];
+ int num_slave_chans;
+ int
Re: [PATCH v2 1/3] dmaengine: add TI EDMA DMA engine driver
On Wed, Aug 22, 2012 at 09:09:26AM +0530, Vinod Koul wrote:
On Tue, 2012-08-21 at 14:43 -0400, Matt Porter wrote:
Add a DMA engine driver for the TI EDMA controller. This driver
is implemented as a wrapper around the existing DaVinci private
DMA implementation. This approach allows for incremental conversion
of each peripheral driver to the DMA engine API. The EDMA driver
supports slave transfers but does not yet support cyclic transfers.
Signed-off-by: Matt Porter mpor...@ti.com
mostly looks decent and in shape.
ok, thanks for the review. I'll be addressing these comments in v3.
Should happen before I go on holiday for the next week.
---
+config TI_EDMA
+ tristate TI EDMA support
+ depends on ARCH_DAVINCI
+ select DMA_ENGINE
+ select DMA_VIRTUAL_CHANNELS
+ default y
default should be n for new drivers
ok
+ help
+ Enable support for the TI EDMA controller. This DMA
+ engine is found on TI DaVinci and AM33xx parts.
+
config ARCH_HAS_ASYNC_TX_FIND_CHANNEL
bool
+/* Max of 16 segments per channel to conserve PaRAM slots */
+#define MAX_NR_SG 16
+#define EDMA_MAX_SLOTS MAX_NR_SG
+#define EDMA_DESCRIPTORS 16
+
+struct edma_desc {
+ struct virt_dma_descvdesc;
+ struct list_headnode;
+
dummy space?
will remove
+ int absync;
+ int pset_nr;
+ struct edmacc_param pset[0];
+};
+
+struct edma_cc;
+
+struct edma_chan {
+ struct virt_dma_chanvchan;
+ struct list_headnode;
+ struct edma_desc*edesc;
+ struct edma_cc *ecc;
+ int ch_num;
+ boolalloced;
+ int slot[EDMA_MAX_SLOTS];
+
+ dma_addr_t addr;
+ int addr_width;
+ int maxburst;
+};
+
+/* Dispatch a queued descriptor to the controller (caller holds lock) */
+static void edma_execute(struct edma_chan *echan)
+{
+ struct virt_dma_desc *vdesc = vchan_next_desc(echan-vchan);
+ struct edma_desc *edesc;
+ int i;
+
+ if (!vdesc) {
+ echan-edesc = NULL;
+ return;
+ }
+
+ list_del(vdesc-node);
+
+ echan-edesc = edesc = to_edma_desc(vdesc-tx);
+
+ /* Write descriptor PaRAM set(s) */
+ for (i = 0; i edesc-pset_nr; i++) {
+ edma_write_slot(echan-slot[i], edesc-pset[i]);
+ dev_dbg(echan-vchan.chan.device-dev,
+ \n pset[%d]:\n
+ chnum\t%d\n
+ slot\t%d\n
+ opt\t%08x\n
+ src\t%08x\n
+ dst\t%08x\n
+ abcnt\t%08x\n
+ ccnt\t%08x\n
+ bidx\t%08x\n
+ cidx\t%08x\n
+ lkrld\t%08x\n,
+ i, echan-ch_num, echan-slot[i],
+ edesc-pset[i].opt,
+ edesc-pset[i].src,
+ edesc-pset[i].dst,
+ edesc-pset[i].a_b_cnt,
+ edesc-pset[i].ccnt,
+ edesc-pset[i].src_dst_bidx,
+ edesc-pset[i].src_dst_cidx,
+ edesc-pset[i].link_bcntrld);
+ /* Link to the previous slot if not the last set */
+ if (i != (edesc-pset_nr - 1))
+ edma_link(echan-slot[i], echan-slot[i+1]);
+ /* Final pset links to the dummy pset */
+ else
+ edma_link(echan-slot[i], echan-ecc-dummy_slot);
+ }
+
+ edma_start(echan-ch_num);
+}
+
+static int edma_terminate_all(struct edma_chan *echan)
+{
+ unsigned long flags;
+ LIST_HEAD(head);
+
+ spin_lock_irqsave(echan-vchan.lock, flags);
+
+ /*
+* Stop DMA activity: we assume the callback will not be called
+* after edma_dma() returns (even if it does, it will see
+* echan-edesc is NULL and exit.)
+*/
+ if (echan-edesc) {
+ echan-edesc = NULL;
+ edma_stop(echan-ch_num);
+ }
+
+ vchan_get_all_descriptors(echan-vchan, head);
+ spin_unlock_irqrestore(echan-vchan.lock, flags);
+ vchan_dma_desc_free_list(echan-vchan, head);
+
+ return 0;
+}
+
+
+static int edma_slave_config(struct edma_chan *echan,
+ struct dma_slave_config *config)
+{
+ if ((config-src_addr_width DMA_SLAVE_BUSWIDTH_4_BYTES) ||
+ (config-dst_addr_width DMA_SLAVE_BUSWIDTH_4_BYTES))
+ return -EINVAL;
the indent needs help here
ok
+
+ if (config-direction == DMA_MEM_TO_DEV) {
+ if (config-dst_addr)
+ echan-addr = config-dst_addr;
+ if
Re: [PATCH v2 1/3] dmaengine: add TI EDMA DMA engine driver
On Wed, Aug 22, 2012 at 12:37:18PM +, Hebbar, Gururaja wrote: On Wed, Aug 22, 2012 at 00:13:07, Porter, Matt wrote: Add a DMA engine driver for the TI EDMA controller. This driver is implemented as a wrapper around the existing DaVinci private DMA implementation. This approach allows for incremental conversion of each peripheral driver to the DMA engine API. The EDMA driver supports slave transfers but does not yet support cyclic transfers. Signed-off-by: Matt Porter mpor...@ti.com --- drivers/dma/Kconfig | 10 + drivers/dma/Makefile |1 + drivers/dma/edma.c | 684 ++ include/linux/edma.h | 29 +++ 4 files changed, 724 insertions(+) create mode 100644 drivers/dma/edma.c create mode 100644 include/linux/edma.h diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index d06ea29..5064e85 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -208,6 +208,16 @@ config SIRF_DMA help Enable support for the CSR SiRFprimaII DMA engine. +config TI_EDMA + tristate TI EDMA support + depends on ARCH_DAVINCI + select DMA_ENGINE + select DMA_VIRTUAL_CHANNELS + default y + help + Enable support for the TI EDMA controller. This DMA + engine is found on TI DaVinci and AM33xx parts. + config ARCH_HAS_ASYNC_TX_FIND_CHANNEL bool diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile index 4cf6b12..f5cf310 100644 --- a/drivers/dma/Makefile +++ b/drivers/dma/Makefile @@ -23,6 +23,7 @@ obj-$(CONFIG_IMX_DMA) += imx-dma.o obj-$(CONFIG_MXS_DMA) += mxs-dma.o obj-$(CONFIG_TIMB_DMA) += timb_dma.o obj-$(CONFIG_SIRF_DMA) += sirf-dma.o +obj-$(CONFIG_TI_EDMA) += edma.o obj-$(CONFIG_STE_DMA40) += ste_dma40.o ste_dma40_ll.o obj-$(CONFIG_TEGRA20_APB_DMA) += tegra20-apb-dma.o obj-$(CONFIG_PL330_DMA) += pl330.o diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c new file mode 100644 index 000..bf15f81 --- /dev/null +++ b/drivers/dma/edma.c @@ -0,0 +1,684 @@ +/* + * TI EDMA DMA engine driver + * + * Copyright 2012 Texas Instruments + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed as is WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include linux/dmaengine.h +#include linux/dma-mapping.h +#include linux/err.h +#include linux/init.h +#include linux/interrupt.h +#include linux/list.h +#include linux/module.h +#include linux/platform_device.h +#include linux/slab.h +#include linux/spinlock.h + +#include mach/edma.h + +#include dmaengine.h +#include virt-dma.h + +/* + * This will go away when the private EDMA API is folded + * into this driver and the platform device(s) are + * instantiated in the arch code. We can only get away + * with this simplification because DA8XX may not be built + * in the same kernel image with other DaVinci parts. This + * avoids having to sprinkle dmaengine driver platform devices + * and data throughout all the existing board files. + */ +#ifdef CONFIG_ARCH_DAVINCI_DA8XX +#define EDMA_CTLRS 2 +#define EDMA_CHANS 32 +#else +#define EDMA_CTLRS 1 +#define EDMA_CHANS 64 +#endif /* CONFIG_ARCH_DAVINCI_DA8XX */ I believe you already have some modifications for your next version to handle Different EDMA IP versions (AM335x). They use/have cross-bar implementations as-well. I don't have those yet. That effort is a WIP atm. However, I should probably add more details to the approach I mentioned in the cover letter for this series. AM335x support will happen by migrating the private EDMA API to arm/common/. There's an incremental change to the private EDMA API implementation to handle AM335x's cross-bar support that exists right now only in the TI vendor tree. I'm going to add that, align the platform devices generated from hwmod data with the existing private EDMA driver expectations, and also add the DT bindings necessary to communicate all the hardware config that's currently carried in the mach-davinci/ board files. That will enable the private EDMA API on AM335x. What I have pushed so far to my WIP branch is: https://github.com/ohporter/linux/tree/WIP/edma-dmaengine-private-migration Completely non-functional on AM335x, but you can at least see where I'm going there. I'm working on the pdev/pdata/DT part mentioned above atm. In turn, since this driver is completely self-contained and sits only on top of the private EDMA API, it will then work on AM335x. This approach avoids having to first convert the remaining McASP driver
Re: [PATCH v2 1/3] dmaengine: add TI EDMA DMA engine driver
On Tue, 2012-08-21 at 14:43 -0400, Matt Porter wrote:
> Add a DMA engine driver for the TI EDMA controller. This driver
> is implemented as a wrapper around the existing DaVinci private
> DMA implementation. This approach allows for incremental conversion
> of each peripheral driver to the DMA engine API. The EDMA driver
> supports slave transfers but does not yet support cyclic transfers.
>
> Signed-off-by: Matt Porter
mostly looks decent and in shape.
> ---
> +config TI_EDMA
> + tristate "TI EDMA support"
> + depends on ARCH_DAVINCI
> + select DMA_ENGINE
> + select DMA_VIRTUAL_CHANNELS
> + default y
default should be n for new drivers
> + help
> + Enable support for the TI EDMA controller. This DMA
> + engine is found on TI DaVinci and AM33xx parts.
> +
> config ARCH_HAS_ASYNC_TX_FIND_CHANNEL
> bool
>
> +/* Max of 16 segments per channel to conserve PaRAM slots */
> +#define MAX_NR_SG16
> +#define EDMA_MAX_SLOTS MAX_NR_SG
> +#define EDMA_DESCRIPTORS 16
> +
> +struct edma_desc {
> + struct virt_dma_descvdesc;
> + struct list_headnode;
> +
dummy space?
> + int absync;
> + int pset_nr;
> + struct edmacc_param pset[0];
> +};
> +
> +struct edma_cc;
> +
> +struct edma_chan {
> + struct virt_dma_chanvchan;
> + struct list_headnode;
> + struct edma_desc*edesc;
> + struct edma_cc *ecc;
> + int ch_num;
> + boolalloced;
> + int slot[EDMA_MAX_SLOTS];
> +
> + dma_addr_t addr;
> + int addr_width;
> + int maxburst;
> +};
> +
> +/* Dispatch a queued descriptor to the controller (caller holds lock) */
> +static void edma_execute(struct edma_chan *echan)
> +{
> + struct virt_dma_desc *vdesc = vchan_next_desc(>vchan);
> + struct edma_desc *edesc;
> + int i;
> +
> + if (!vdesc) {
> + echan->edesc = NULL;
> + return;
> + }
> +
> + list_del(>node);
> +
> + echan->edesc = edesc = to_edma_desc(>tx);
> +
> + /* Write descriptor PaRAM set(s) */
> + for (i = 0; i < edesc->pset_nr; i++) {
> + edma_write_slot(echan->slot[i], >pset[i]);
> + dev_dbg(echan->vchan.chan.device->dev,
> + "\n pset[%d]:\n"
> + " chnum\t%d\n"
> + " slot\t%d\n"
> + " opt\t%08x\n"
> + " src\t%08x\n"
> + " dst\t%08x\n"
> + " abcnt\t%08x\n"
> + " ccnt\t%08x\n"
> + " bidx\t%08x\n"
> + " cidx\t%08x\n"
> + " lkrld\t%08x\n",
> + i, echan->ch_num, echan->slot[i],
> + edesc->pset[i].opt,
> + edesc->pset[i].src,
> + edesc->pset[i].dst,
> + edesc->pset[i].a_b_cnt,
> + edesc->pset[i].ccnt,
> + edesc->pset[i].src_dst_bidx,
> + edesc->pset[i].src_dst_cidx,
> + edesc->pset[i].link_bcntrld);
> + /* Link to the previous slot if not the last set */
> + if (i != (edesc->pset_nr - 1))
> + edma_link(echan->slot[i], echan->slot[i+1]);
> + /* Final pset links to the dummy pset */
> + else
> + edma_link(echan->slot[i], echan->ecc->dummy_slot);
> + }
> +
> + edma_start(echan->ch_num);
> +}
> +
> +static int edma_terminate_all(struct edma_chan *echan)
> +{
> + unsigned long flags;
> + LIST_HEAD(head);
> +
> + spin_lock_irqsave(>vchan.lock, flags);
> +
> + /*
> + * Stop DMA activity: we assume the callback will not be called
> + * after edma_dma() returns (even if it does, it will see
> + * echan->edesc is NULL and exit.)
> + */
> + if (echan->edesc) {
> + echan->edesc = NULL;
> + edma_stop(echan->ch_num);
> + }
> +
> + vchan_get_all_descriptors(>vchan, );
> + spin_unlock_irqrestore(>vchan.lock, flags);
> + vchan_dma_desc_free_list(>vchan, );
> +
> + return 0;
> +}
> +
> +
> +static int edma_slave_config(struct edma_chan *echan,
> + struct dma_slave_config *config)
> +{
> + if ((config->src_addr_width > DMA_SLAVE_BUSWIDTH_4_BYTES) ||
> + (config->dst_addr_width > DMA_SLAVE_BUSWIDTH_4_BYTES))
> + return -EINVAL;
the indent needs help here
> +
> + if (config->direction == DMA_MEM_TO_DEV) {
> + if (config->dst_addr)
> + echan->addr = config->dst_addr;
> + if (config->dst_addr_width)
> +
[PATCH v2 1/3] dmaengine: add TI EDMA DMA engine driver
Add a DMA engine driver for the TI EDMA controller. This driver
is implemented as a wrapper around the existing DaVinci private
DMA implementation. This approach allows for incremental conversion
of each peripheral driver to the DMA engine API. The EDMA driver
supports slave transfers but does not yet support cyclic transfers.
Signed-off-by: Matt Porter
---
drivers/dma/Kconfig | 10 +
drivers/dma/Makefile |1 +
drivers/dma/edma.c | 684 ++
include/linux/edma.h | 29 +++
4 files changed, 724 insertions(+)
create mode 100644 drivers/dma/edma.c
create mode 100644 include/linux/edma.h
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index d06ea29..5064e85 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -208,6 +208,16 @@ config SIRF_DMA
help
Enable support for the CSR SiRFprimaII DMA engine.
+config TI_EDMA
+ tristate "TI EDMA support"
+ depends on ARCH_DAVINCI
+ select DMA_ENGINE
+ select DMA_VIRTUAL_CHANNELS
+ default y
+ help
+ Enable support for the TI EDMA controller. This DMA
+ engine is found on TI DaVinci and AM33xx parts.
+
config ARCH_HAS_ASYNC_TX_FIND_CHANNEL
bool
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index 4cf6b12..f5cf310 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -23,6 +23,7 @@ obj-$(CONFIG_IMX_DMA) += imx-dma.o
obj-$(CONFIG_MXS_DMA) += mxs-dma.o
obj-$(CONFIG_TIMB_DMA) += timb_dma.o
obj-$(CONFIG_SIRF_DMA) += sirf-dma.o
+obj-$(CONFIG_TI_EDMA) += edma.o
obj-$(CONFIG_STE_DMA40) += ste_dma40.o ste_dma40_ll.o
obj-$(CONFIG_TEGRA20_APB_DMA) += tegra20-apb-dma.o
obj-$(CONFIG_PL330_DMA) += pl330.o
diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c
new file mode 100644
index 000..bf15f81
--- /dev/null
+++ b/drivers/dma/edma.c
@@ -0,0 +1,684 @@
+/*
+ * TI EDMA DMA engine driver
+ *
+ * Copyright 2012 Texas Instruments
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#include "dmaengine.h"
+#include "virt-dma.h"
+
+/*
+ * This will go away when the private EDMA API is folded
+ * into this driver and the platform device(s) are
+ * instantiated in the arch code. We can only get away
+ * with this simplification because DA8XX may not be built
+ * in the same kernel image with other DaVinci parts. This
+ * avoids having to sprinkle dmaengine driver platform devices
+ * and data throughout all the existing board files.
+ */
+#ifdef CONFIG_ARCH_DAVINCI_DA8XX
+#define EDMA_CTLRS 2
+#define EDMA_CHANS 32
+#else
+#define EDMA_CTLRS 1
+#define EDMA_CHANS 64
+#endif /* CONFIG_ARCH_DAVINCI_DA8XX */
+
+/* Max of 16 segments per channel to conserve PaRAM slots */
+#define MAX_NR_SG 16
+#define EDMA_MAX_SLOTS MAX_NR_SG
+#define EDMA_DESCRIPTORS 16
+
+struct edma_desc {
+ struct virt_dma_descvdesc;
+ struct list_headnode;
+
+ int absync;
+ int pset_nr;
+ struct edmacc_param pset[0];
+};
+
+struct edma_cc;
+
+struct edma_chan {
+ struct virt_dma_chanvchan;
+ struct list_headnode;
+ struct edma_desc*edesc;
+ struct edma_cc *ecc;
+ int ch_num;
+ boolalloced;
+ int slot[EDMA_MAX_SLOTS];
+
+ dma_addr_t addr;
+ int addr_width;
+ int maxburst;
+};
+
+struct edma_cc {
+ int ctlr;
+ struct dma_device dma_slave;
+ struct edma_chanslave_chans[EDMA_CHANS];
+ int num_slave_chans;
+ int dummy_slot;
+};
+
+static inline struct edma_cc *to_edma_cc(struct dma_device *d)
+{
+ return container_of(d, struct edma_cc, dma_slave);
+}
+
+static inline struct edma_chan *to_edma_chan(struct dma_chan *c)
+{
+ return container_of(c, struct edma_chan, vchan.chan);
+}
+
+static inline struct edma_desc
+*to_edma_desc(struct dma_async_tx_descriptor *tx)
+{
+ return container_of(tx, struct edma_desc, vdesc.tx);
+}
+
+static void edma_desc_free(struct virt_dma_desc *vdesc)
+{
+ kfree(container_of(vdesc,
Re: [PATCH v2 1/3] dmaengine: add TI EDMA DMA engine driver
On Tue, 2012-08-21 at 14:43 -0400, Matt Porter wrote:
Add a DMA engine driver for the TI EDMA controller. This driver
is implemented as a wrapper around the existing DaVinci private
DMA implementation. This approach allows for incremental conversion
of each peripheral driver to the DMA engine API. The EDMA driver
supports slave transfers but does not yet support cyclic transfers.
Signed-off-by: Matt Porter mpor...@ti.com
mostly looks decent and in shape.
---
+config TI_EDMA
+ tristate TI EDMA support
+ depends on ARCH_DAVINCI
+ select DMA_ENGINE
+ select DMA_VIRTUAL_CHANNELS
+ default y
default should be n for new drivers
+ help
+ Enable support for the TI EDMA controller. This DMA
+ engine is found on TI DaVinci and AM33xx parts.
+
config ARCH_HAS_ASYNC_TX_FIND_CHANNEL
bool
+/* Max of 16 segments per channel to conserve PaRAM slots */
+#define MAX_NR_SG16
+#define EDMA_MAX_SLOTS MAX_NR_SG
+#define EDMA_DESCRIPTORS 16
+
+struct edma_desc {
+ struct virt_dma_descvdesc;
+ struct list_headnode;
+
dummy space?
+ int absync;
+ int pset_nr;
+ struct edmacc_param pset[0];
+};
+
+struct edma_cc;
+
+struct edma_chan {
+ struct virt_dma_chanvchan;
+ struct list_headnode;
+ struct edma_desc*edesc;
+ struct edma_cc *ecc;
+ int ch_num;
+ boolalloced;
+ int slot[EDMA_MAX_SLOTS];
+
+ dma_addr_t addr;
+ int addr_width;
+ int maxburst;
+};
+
+/* Dispatch a queued descriptor to the controller (caller holds lock) */
+static void edma_execute(struct edma_chan *echan)
+{
+ struct virt_dma_desc *vdesc = vchan_next_desc(echan-vchan);
+ struct edma_desc *edesc;
+ int i;
+
+ if (!vdesc) {
+ echan-edesc = NULL;
+ return;
+ }
+
+ list_del(vdesc-node);
+
+ echan-edesc = edesc = to_edma_desc(vdesc-tx);
+
+ /* Write descriptor PaRAM set(s) */
+ for (i = 0; i edesc-pset_nr; i++) {
+ edma_write_slot(echan-slot[i], edesc-pset[i]);
+ dev_dbg(echan-vchan.chan.device-dev,
+ \n pset[%d]:\n
+ chnum\t%d\n
+ slot\t%d\n
+ opt\t%08x\n
+ src\t%08x\n
+ dst\t%08x\n
+ abcnt\t%08x\n
+ ccnt\t%08x\n
+ bidx\t%08x\n
+ cidx\t%08x\n
+ lkrld\t%08x\n,
+ i, echan-ch_num, echan-slot[i],
+ edesc-pset[i].opt,
+ edesc-pset[i].src,
+ edesc-pset[i].dst,
+ edesc-pset[i].a_b_cnt,
+ edesc-pset[i].ccnt,
+ edesc-pset[i].src_dst_bidx,
+ edesc-pset[i].src_dst_cidx,
+ edesc-pset[i].link_bcntrld);
+ /* Link to the previous slot if not the last set */
+ if (i != (edesc-pset_nr - 1))
+ edma_link(echan-slot[i], echan-slot[i+1]);
+ /* Final pset links to the dummy pset */
+ else
+ edma_link(echan-slot[i], echan-ecc-dummy_slot);
+ }
+
+ edma_start(echan-ch_num);
+}
+
+static int edma_terminate_all(struct edma_chan *echan)
+{
+ unsigned long flags;
+ LIST_HEAD(head);
+
+ spin_lock_irqsave(echan-vchan.lock, flags);
+
+ /*
+ * Stop DMA activity: we assume the callback will not be called
+ * after edma_dma() returns (even if it does, it will see
+ * echan-edesc is NULL and exit.)
+ */
+ if (echan-edesc) {
+ echan-edesc = NULL;
+ edma_stop(echan-ch_num);
+ }
+
+ vchan_get_all_descriptors(echan-vchan, head);
+ spin_unlock_irqrestore(echan-vchan.lock, flags);
+ vchan_dma_desc_free_list(echan-vchan, head);
+
+ return 0;
+}
+
+
+static int edma_slave_config(struct edma_chan *echan,
+ struct dma_slave_config *config)
+{
+ if ((config-src_addr_width DMA_SLAVE_BUSWIDTH_4_BYTES) ||
+ (config-dst_addr_width DMA_SLAVE_BUSWIDTH_4_BYTES))
+ return -EINVAL;
the indent needs help here
+
+ if (config-direction == DMA_MEM_TO_DEV) {
+ if (config-dst_addr)
+ echan-addr = config-dst_addr;
+ if (config-dst_addr_width)
+ echan-addr_width = config-dst_addr_width;
+ if (config-dst_maxburst)
+ echan-maxburst =
[PATCH v2 1/3] dmaengine: add TI EDMA DMA engine driver
Add a DMA engine driver for the TI EDMA controller. This driver
is implemented as a wrapper around the existing DaVinci private
DMA implementation. This approach allows for incremental conversion
of each peripheral driver to the DMA engine API. The EDMA driver
supports slave transfers but does not yet support cyclic transfers.
Signed-off-by: Matt Porter mpor...@ti.com
---
drivers/dma/Kconfig | 10 +
drivers/dma/Makefile |1 +
drivers/dma/edma.c | 684 ++
include/linux/edma.h | 29 +++
4 files changed, 724 insertions(+)
create mode 100644 drivers/dma/edma.c
create mode 100644 include/linux/edma.h
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index d06ea29..5064e85 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -208,6 +208,16 @@ config SIRF_DMA
help
Enable support for the CSR SiRFprimaII DMA engine.
+config TI_EDMA
+ tristate TI EDMA support
+ depends on ARCH_DAVINCI
+ select DMA_ENGINE
+ select DMA_VIRTUAL_CHANNELS
+ default y
+ help
+ Enable support for the TI EDMA controller. This DMA
+ engine is found on TI DaVinci and AM33xx parts.
+
config ARCH_HAS_ASYNC_TX_FIND_CHANNEL
bool
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index 4cf6b12..f5cf310 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -23,6 +23,7 @@ obj-$(CONFIG_IMX_DMA) += imx-dma.o
obj-$(CONFIG_MXS_DMA) += mxs-dma.o
obj-$(CONFIG_TIMB_DMA) += timb_dma.o
obj-$(CONFIG_SIRF_DMA) += sirf-dma.o
+obj-$(CONFIG_TI_EDMA) += edma.o
obj-$(CONFIG_STE_DMA40) += ste_dma40.o ste_dma40_ll.o
obj-$(CONFIG_TEGRA20_APB_DMA) += tegra20-apb-dma.o
obj-$(CONFIG_PL330_DMA) += pl330.o
diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c
new file mode 100644
index 000..bf15f81
--- /dev/null
+++ b/drivers/dma/edma.c
@@ -0,0 +1,684 @@
+/*
+ * TI EDMA DMA engine driver
+ *
+ * Copyright 2012 Texas Instruments
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed as is WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include linux/dmaengine.h
+#include linux/dma-mapping.h
+#include linux/err.h
+#include linux/init.h
+#include linux/interrupt.h
+#include linux/list.h
+#include linux/module.h
+#include linux/platform_device.h
+#include linux/slab.h
+#include linux/spinlock.h
+
+#include mach/edma.h
+
+#include dmaengine.h
+#include virt-dma.h
+
+/*
+ * This will go away when the private EDMA API is folded
+ * into this driver and the platform device(s) are
+ * instantiated in the arch code. We can only get away
+ * with this simplification because DA8XX may not be built
+ * in the same kernel image with other DaVinci parts. This
+ * avoids having to sprinkle dmaengine driver platform devices
+ * and data throughout all the existing board files.
+ */
+#ifdef CONFIG_ARCH_DAVINCI_DA8XX
+#define EDMA_CTLRS 2
+#define EDMA_CHANS 32
+#else
+#define EDMA_CTLRS 1
+#define EDMA_CHANS 64
+#endif /* CONFIG_ARCH_DAVINCI_DA8XX */
+
+/* Max of 16 segments per channel to conserve PaRAM slots */
+#define MAX_NR_SG 16
+#define EDMA_MAX_SLOTS MAX_NR_SG
+#define EDMA_DESCRIPTORS 16
+
+struct edma_desc {
+ struct virt_dma_descvdesc;
+ struct list_headnode;
+
+ int absync;
+ int pset_nr;
+ struct edmacc_param pset[0];
+};
+
+struct edma_cc;
+
+struct edma_chan {
+ struct virt_dma_chanvchan;
+ struct list_headnode;
+ struct edma_desc*edesc;
+ struct edma_cc *ecc;
+ int ch_num;
+ boolalloced;
+ int slot[EDMA_MAX_SLOTS];
+
+ dma_addr_t addr;
+ int addr_width;
+ int maxburst;
+};
+
+struct edma_cc {
+ int ctlr;
+ struct dma_device dma_slave;
+ struct edma_chanslave_chans[EDMA_CHANS];
+ int num_slave_chans;
+ int dummy_slot;
+};
+
+static inline struct edma_cc *to_edma_cc(struct dma_device *d)
+{
+ return container_of(d, struct edma_cc, dma_slave);
+}
+
+static inline struct edma_chan *to_edma_chan(struct dma_chan *c)
+{
+ return container_of(c, struct edma_chan, vchan.chan);
+}
+
+static inline struct edma_desc
+*to_edma_desc(struct
