[PATCH v2 16/19] clk: meson: split divider and gate part of mpll

[Jerome Brunet]

The mpll clock is a kind of fractional divider which can gate.
When the RW operation have been added, enable/disable ops have been
mistakenly inserted in this driver. These ops are essentially a
poor copy/paste of the generic gate ops.

This change removes the gate ops from the mpll driver and inserts a
generic gate clock on each mpll divider, simplifying the mpll
driver and reducing code duplication.

Signed-off-by: Jerome Brunet 
---
 drivers/clk/meson/axg.c  | 100 +++
 drivers/clk/meson/axg.h  |   6 ++-
 drivers/clk/meson/clk-mpll.c |  44 ---
 drivers/clk/meson/clkc.h |   1 -
 drivers/clk/meson/gxbb.c |  78 -
 drivers/clk/meson/gxbb.h |   5 ++-
 drivers/clk/meson/meson8b.c  |  75 +++-
 drivers/clk/meson/meson8b.h  |   6 ++-
 8 files changed, 197 insertions(+), 118 deletions(-)

diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c
index 8c27ceffda4a..6813b632c1a9 100644
--- a/drivers/clk/meson/axg.c
+++ b/drivers/clk/meson/axg.c
@@ -296,7 +296,7 @@ static struct clk_fixed_factor axg_fclk_div7 = {
},
 };
 
-static struct clk_regmap axg_mpll0 = {
+static struct clk_regmap axg_mpll0_div = {
.data = &(struct meson_clk_mpll_data){
.sdm = {
.reg_off = HHI_MPLL_CNTL7,
@@ -313,11 +313,6 @@ static struct clk_regmap axg_mpll0 = {
.shift   = 16,
.width   = 9,
},
-   .en = {
-   .reg_off = HHI_MPLL_CNTL7,
-   .shift   = 14,
-   .width   = 1,
-   },
.ssen = {
.reg_off = HHI_MPLL_CNTL,
.shift   = 25,
@@ -331,14 +326,28 @@ static struct clk_regmap axg_mpll0 = {
.lock = _clk_lock,
},
.hw.init = &(struct clk_init_data){
-   .name = "mpll0",
+   .name = "mpll0_div",
.ops = _clk_mpll_ops,
.parent_names = (const char *[]){ "fixed_pll" },
.num_parents = 1,
},
 };
 
-static struct clk_regmap axg_mpll1 = {
+static struct clk_regmap axg_mpll0 = {
+   .data = &(struct clk_regmap_gate_data){
+   .offset = HHI_MPLL_CNTL7,
+   .bit_idx = 14,
+   },
+   .hw.init = &(struct clk_init_data){
+   .name = "mpll0",
+   .ops = _regmap_gate_ops,
+   .parent_names = (const char *[]){ "mpll0_div" },
+   .num_parents = 1,
+   .flags = CLK_SET_RATE_PARENT,
+   },
+};
+
+static struct clk_regmap axg_mpll1_div = {
.data = &(struct meson_clk_mpll_data){
.sdm = {
.reg_off = HHI_MPLL_CNTL8,
@@ -355,11 +364,6 @@ static struct clk_regmap axg_mpll1 = {
.shift   = 16,
.width   = 9,
},
-   .en = {
-   .reg_off = HHI_MPLL_CNTL8,
-   .shift   = 14,
-   .width   = 1,
-   },
.misc = {
.reg_off = HHI_PLL_TOP_MISC,
.shift   = 1,
@@ -368,14 +372,28 @@ static struct clk_regmap axg_mpll1 = {
.lock = _clk_lock,
},
.hw.init = &(struct clk_init_data){
-   .name = "mpll1",
+   .name = "mpll1_div",
.ops = _clk_mpll_ops,
.parent_names = (const char *[]){ "fixed_pll" },
.num_parents = 1,
},
 };
 
-static struct clk_regmap axg_mpll2 = {
+static struct clk_regmap axg_mpll1 = {
+   .data = &(struct clk_regmap_gate_data){
+   .offset = HHI_MPLL_CNTL8,
+   .bit_idx = 14,
+   },
+   .hw.init = &(struct clk_init_data){
+   .name = "mpll1",
+   .ops = _regmap_gate_ops,
+   .parent_names = (const char *[]){ "mpll1_div" },
+   .num_parents = 1,
+   .flags = CLK_SET_RATE_PARENT,
+   },
+};
+
+static struct clk_regmap axg_mpll2_div = {
.data = &(struct meson_clk_mpll_data){
.sdm = {
.reg_off = HHI_MPLL_CNTL9,
@@ -392,11 +410,6 @@ static struct clk_regmap axg_mpll2 = {
.shift   = 16,
.width   = 9,
},
-   .en = {
-   .reg_off = HHI_MPLL_CNTL9,
-   .shift   = 14,
-   .width   = 1,
-   },
.misc = {
.reg_off = HHI_PLL_TOP_MISC,
.shift   = 2,
@@ -405,14 +418,28 @@ static struct clk_regmap axg_mpll2 = {
.lock = _clk_lock,
},
.hw.init = &(struct clk_init_data){
-   .name = "mpll2",
+  

[PATCH v2 16/19] clk: meson: split divider and gate part of mpll

[Jerome Brunet]

The mpll clock is a kind of fractional divider which can gate.
When the RW operation have been added, enable/disable ops have been
mistakenly inserted in this driver. These ops are essentially a
poor copy/paste of the generic gate ops.

This change removes the gate ops from the mpll driver and inserts a
generic gate clock on each mpll divider, simplifying the mpll
driver and reducing code duplication.

Signed-off-by: Jerome Brunet 
---
 drivers/clk/meson/axg.c  | 100 +++
 drivers/clk/meson/axg.h  |   6 ++-
 drivers/clk/meson/clk-mpll.c |  44 ---
 drivers/clk/meson/clkc.h |   1 -
 drivers/clk/meson/gxbb.c |  78 -
 drivers/clk/meson/gxbb.h |   5 ++-
 drivers/clk/meson/meson8b.c  |  75 +++-
 drivers/clk/meson/meson8b.h  |   6 ++-
 8 files changed, 197 insertions(+), 118 deletions(-)

diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c
index 8c27ceffda4a..6813b632c1a9 100644
--- a/drivers/clk/meson/axg.c
+++ b/drivers/clk/meson/axg.c
@@ -296,7 +296,7 @@ static struct clk_fixed_factor axg_fclk_div7 = {
},
 };
 
-static struct clk_regmap axg_mpll0 = {
+static struct clk_regmap axg_mpll0_div = {
.data = &(struct meson_clk_mpll_data){
.sdm = {
.reg_off = HHI_MPLL_CNTL7,
@@ -313,11 +313,6 @@ static struct clk_regmap axg_mpll0 = {
.shift   = 16,
.width   = 9,
},
-   .en = {
-   .reg_off = HHI_MPLL_CNTL7,
-   .shift   = 14,
-   .width   = 1,
-   },
.ssen = {
.reg_off = HHI_MPLL_CNTL,
.shift   = 25,
@@ -331,14 +326,28 @@ static struct clk_regmap axg_mpll0 = {
.lock = _clk_lock,
},
.hw.init = &(struct clk_init_data){
-   .name = "mpll0",
+   .name = "mpll0_div",
.ops = _clk_mpll_ops,
.parent_names = (const char *[]){ "fixed_pll" },
.num_parents = 1,
},
 };
 
-static struct clk_regmap axg_mpll1 = {
+static struct clk_regmap axg_mpll0 = {
+   .data = &(struct clk_regmap_gate_data){
+   .offset = HHI_MPLL_CNTL7,
+   .bit_idx = 14,
+   },
+   .hw.init = &(struct clk_init_data){
+   .name = "mpll0",
+   .ops = _regmap_gate_ops,
+   .parent_names = (const char *[]){ "mpll0_div" },
+   .num_parents = 1,
+   .flags = CLK_SET_RATE_PARENT,
+   },
+};
+
+static struct clk_regmap axg_mpll1_div = {
.data = &(struct meson_clk_mpll_data){
.sdm = {
.reg_off = HHI_MPLL_CNTL8,
@@ -355,11 +364,6 @@ static struct clk_regmap axg_mpll1 = {
.shift   = 16,
.width   = 9,
},
-   .en = {
-   .reg_off = HHI_MPLL_CNTL8,
-   .shift   = 14,
-   .width   = 1,
-   },
.misc = {
.reg_off = HHI_PLL_TOP_MISC,
.shift   = 1,
@@ -368,14 +372,28 @@ static struct clk_regmap axg_mpll1 = {
.lock = _clk_lock,
},
.hw.init = &(struct clk_init_data){
-   .name = "mpll1",
+   .name = "mpll1_div",
.ops = _clk_mpll_ops,
.parent_names = (const char *[]){ "fixed_pll" },
.num_parents = 1,
},
 };
 
-static struct clk_regmap axg_mpll2 = {
+static struct clk_regmap axg_mpll1 = {
+   .data = &(struct clk_regmap_gate_data){
+   .offset = HHI_MPLL_CNTL8,
+   .bit_idx = 14,
+   },
+   .hw.init = &(struct clk_init_data){
+   .name = "mpll1",
+   .ops = _regmap_gate_ops,
+   .parent_names = (const char *[]){ "mpll1_div" },
+   .num_parents = 1,
+   .flags = CLK_SET_RATE_PARENT,
+   },
+};
+
+static struct clk_regmap axg_mpll2_div = {
.data = &(struct meson_clk_mpll_data){
.sdm = {
.reg_off = HHI_MPLL_CNTL9,
@@ -392,11 +410,6 @@ static struct clk_regmap axg_mpll2 = {
.shift   = 16,
.width   = 9,
},
-   .en = {
-   .reg_off = HHI_MPLL_CNTL9,
-   .shift   = 14,
-   .width   = 1,
-   },
.misc = {
.reg_off = HHI_PLL_TOP_MISC,
.shift   = 2,
@@ -405,14 +418,28 @@ static struct clk_regmap axg_mpll2 = {
.lock = _clk_lock,
},
.hw.init = &(struct clk_init_data){
-   .name = "mpll2",
+   .name =