Re: [PATCH v2 2/2] spi: spi-pic32: Add PIC32 SPI master driver

2016-03-05 Thread Mark Brown 
On Sat, Mar 05, 2016 at 08:45:22PM +0530, Purna Chandra Mandal wrote:

> Sorry Mark.
> I have missed adding you in CC. Please find it from:

> https://lkml.org/lkml/2016/3/4/401

No, I can't review or apply patches from a web link - please resend.


signature.asc
Description: PGP signature

Re: [PATCH v2 2/2] spi: spi-pic32: Add PIC32 SPI master driver

2016-03-05 Thread Mark Brown 
On Sat, Mar 05, 2016 at 08:45:22PM +0530, Purna Chandra Mandal wrote:

> Sorry Mark.
> I have missed adding you in CC. Please find it from:

> https://lkml.org/lkml/2016/3/4/401

No, I can't review or apply patches from a web link - please resend.


signature.asc
Description: PGP signature

Re: [PATCH v2 2/2] spi: spi-pic32: Add PIC32 SPI master driver

2016-03-05 Thread Purna Chandra Mandal 
On 03/05/2016 09:10 AM, Mark Brown wrote:

> On Fri, Mar 04, 2016 at 07:14:42PM +0530, Purna Chandra Mandal wrote:
>> The PIC32 SPI driver is capable of performing SPI transfers
>> using PIO or external DMA engine. GPIO controlled /CS support
> I don't seem to have patch 1 in this series.

Sorry Mark.
I have missed adding you in CC. Please find it from:

https://lkml.org/lkml/2016/3/4/401

--Purna

Re: [PATCH v2 2/2] spi: spi-pic32: Add PIC32 SPI master driver

2016-03-05 Thread Purna Chandra Mandal 
On 03/05/2016 09:10 AM, Mark Brown wrote:

> On Fri, Mar 04, 2016 at 07:14:42PM +0530, Purna Chandra Mandal wrote:
>> The PIC32 SPI driver is capable of performing SPI transfers
>> using PIO or external DMA engine. GPIO controlled /CS support
> I don't seem to have patch 1 in this series.

Sorry Mark.
I have missed adding you in CC. Please find it from:

https://lkml.org/lkml/2016/3/4/401

--Purna

Re: [PATCH v2 2/2] spi: spi-pic32: Add PIC32 SPI master driver

2016-03-05 Thread Mark Brown 
On Fri, Mar 04, 2016 at 07:14:42PM +0530, Purna Chandra Mandal wrote:
> The PIC32 SPI driver is capable of performing SPI transfers
> using PIO or external DMA engine. GPIO controlled /CS support

I don't seem to have patch 1 in this series.


signature.asc
Description: PGP signature

Re: [PATCH v2 2/2] spi: spi-pic32: Add PIC32 SPI master driver

2016-03-05 Thread Mark Brown 
On Fri, Mar 04, 2016 at 07:14:42PM +0530, Purna Chandra Mandal wrote:
> The PIC32 SPI driver is capable of performing SPI transfers
> using PIO or external DMA engine. GPIO controlled /CS support

I don't seem to have patch 1 in this series.


signature.asc
Description: PGP signature

Re: [PATCH v2 2/2] spi: spi-pic32: Add PIC32 SPI master driver

2016-03-04 Thread kbuild test robot 
Hi Purna,

[auto build test WARNING on robh/for-next]
[also build test WARNING on v4.5-rc6 next-20160304]
[cannot apply to spi/for-next]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improving the system]

url:
https://github.com/0day-ci/linux/commits/Purna-Chandra-Mandal/dt-bindings-Add-bindings-for-PIC32-SPI-peripheral/20160304-214814
base:   https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux for-next
config: sparc64-allmodconfig (attached as .config)
reproduce:
wget 
https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross
 -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=sparc64 

All warnings (new ones prefixed by >>):

   In file included from include/linux/dmaengine.h:20:0,
from drivers/spi/spi-pic32.c:20:
   drivers/spi/spi-pic32.c: In function 'pic32_spi_dma_transfer':
>> drivers/spi/spi-pic32.c:392:18: warning: cast to pointer from integer of 
>> different size [-Wint-to-pointer-cast]
   xfer->tx_buf, (void *)xfer->tx_dma,
 ^
   include/linux/device.h:1286:41: note: in definition of macro 'dev_vdbg'
  dev_printk(KERN_DEBUG, dev, format, ##arg); \
^
   drivers/spi/spi-pic32.c:393:18: warning: cast to pointer from integer of 
different size [-Wint-to-pointer-cast]
   xfer->rx_buf, (void *)xfer->rx_dma);
 ^
   include/linux/device.h:1286:41: note: in definition of macro 'dev_vdbg'
  dev_printk(KERN_DEBUG, dev, format, ##arg); \
^

vim +392 drivers/spi/spi-pic32.c

   376  ret = -EINVAL;
   377  goto err_dma;
   378  }
   379  
   380  desc_tx = dmaengine_prep_slave_sg(master->dma_tx,
   381xfer->tx_sg.sgl,
   382xfer->tx_sg.nents,
   383DMA_TO_DEVICE,
   384DMA_PREP_INTERRUPT | 
DMA_CTRL_ACK);
   385  if (!desc_tx) {
   386  ret = -EINVAL;
   387  goto err_dma;
   388  }
   389  
   390  dev_vdbg(>dev, "dma_xfer %p: len %u, tx %p(%p), rx 
%p(%p)\n",
   391   xfer, xfer->len,
 > 392   xfer->tx_buf, (void *)xfer->tx_dma,
   393   xfer->rx_buf, (void *)xfer->rx_dma);
   394  
   395  /* Put callback on the RX transfer, that should finish last */
   396  desc_rx->callback = pic32_spi_dma_rx_notify;
   397  desc_rx->callback_param = pic32s;
   398  
   399  cookie = dmaengine_submit(desc_rx);
   400  ret = dma_submit_error(cookie);

---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all   Intel Corporation


.config.gz
Description: Binary data

Re: [PATCH v2 2/2] spi: spi-pic32: Add PIC32 SPI master driver

2016-03-04 Thread kbuild test robot 
Hi Purna,

[auto build test WARNING on robh/for-next]
[also build test WARNING on v4.5-rc6 next-20160304]
[cannot apply to spi/for-next]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improving the system]

url:
https://github.com/0day-ci/linux/commits/Purna-Chandra-Mandal/dt-bindings-Add-bindings-for-PIC32-SPI-peripheral/20160304-214814
base:   https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux for-next
config: sparc64-allmodconfig (attached as .config)
reproduce:
wget 
https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross
 -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=sparc64 

All warnings (new ones prefixed by >>):

   In file included from include/linux/dmaengine.h:20:0,
from drivers/spi/spi-pic32.c:20:
   drivers/spi/spi-pic32.c: In function 'pic32_spi_dma_transfer':
>> drivers/spi/spi-pic32.c:392:18: warning: cast to pointer from integer of 
>> different size [-Wint-to-pointer-cast]
   xfer->tx_buf, (void *)xfer->tx_dma,
 ^
   include/linux/device.h:1286:41: note: in definition of macro 'dev_vdbg'
  dev_printk(KERN_DEBUG, dev, format, ##arg); \
^
   drivers/spi/spi-pic32.c:393:18: warning: cast to pointer from integer of 
different size [-Wint-to-pointer-cast]
   xfer->rx_buf, (void *)xfer->rx_dma);
 ^
   include/linux/device.h:1286:41: note: in definition of macro 'dev_vdbg'
  dev_printk(KERN_DEBUG, dev, format, ##arg); \
^

vim +392 drivers/spi/spi-pic32.c

   376  ret = -EINVAL;
   377  goto err_dma;
   378  }
   379  
   380  desc_tx = dmaengine_prep_slave_sg(master->dma_tx,
   381xfer->tx_sg.sgl,
   382xfer->tx_sg.nents,
   383DMA_TO_DEVICE,
   384DMA_PREP_INTERRUPT | 
DMA_CTRL_ACK);
   385  if (!desc_tx) {
   386  ret = -EINVAL;
   387  goto err_dma;
   388  }
   389  
   390  dev_vdbg(>dev, "dma_xfer %p: len %u, tx %p(%p), rx 
%p(%p)\n",
   391   xfer, xfer->len,
 > 392   xfer->tx_buf, (void *)xfer->tx_dma,
   393   xfer->rx_buf, (void *)xfer->rx_dma);
   394  
   395  /* Put callback on the RX transfer, that should finish last */
   396  desc_rx->callback = pic32_spi_dma_rx_notify;
   397  desc_rx->callback_param = pic32s;
   398  
   399  cookie = dmaengine_submit(desc_rx);
   400  ret = dma_submit_error(cookie);

---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all   Intel Corporation


.config.gz
Description: Binary data

Re: [PATCH v2 2/2] spi: spi-pic32: Add PIC32 SPI master driver

2016-03-04 Thread kbuild test robot 
Hi Purna,

[auto build test WARNING on robh/for-next]
[also build test WARNING on v4.5-rc6 next-20160303]
[cannot apply to spi/for-next]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improving the system]

url:
https://github.com/0day-ci/linux/commits/Purna-Chandra-Mandal/dt-bindings-Add-bindings-for-PIC32-SPI-peripheral/20160304-214814
base:   https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux for-next


coccinelle warnings: (new ones prefixed by >>)

>> drivers/spi/spi-pic32.c:993:3-8: No need to set .owner here. The core will 
>> do it.

Please review and possibly fold the followup patch.

---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all   Intel Corporation

Re: [PATCH v2 2/2] spi: spi-pic32: Add PIC32 SPI master driver

2016-03-04 Thread kbuild test robot 
Hi Purna,

[auto build test WARNING on robh/for-next]
[also build test WARNING on v4.5-rc6 next-20160303]
[cannot apply to spi/for-next]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improving the system]

url:
https://github.com/0day-ci/linux/commits/Purna-Chandra-Mandal/dt-bindings-Add-bindings-for-PIC32-SPI-peripheral/20160304-214814
base:   https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux for-next


coccinelle warnings: (new ones prefixed by >>)

>> drivers/spi/spi-pic32.c:993:3-8: No need to set .owner here. The core will 
>> do it.

Please review and possibly fold the followup patch.

---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all   Intel Corporation

[PATCH v2 2/2] spi: spi-pic32: Add PIC32 SPI master driver

2016-03-04 Thread Purna Chandra Mandal 
The PIC32 SPI driver is capable of performing SPI transfers
using PIO or external DMA engine. GPIO controlled /CS support
is made default in the driver for correct operation of the
controller. This can be enabled by adding "cs-gpios" property
of the SPI node in board dts file.

Signed-off-by: Purna Chandra Mandal 

---

Changes in v2:
- drop internal function drain_rx_fifo()
- merge wrapper functions with callers wherever applicable
- sort includes alphabetically
- Kconfig: sort SPI_PIC32 alphabetically and add || COMPILE_TEST
- Makefile: sort SPI_PIC32 alphabetically
- replace cpu_relax() with ndelay() in disable_chip()
- drop spi controller driven /CS management completely, use only
  GPIO controller /CS.
- rename function names starting with 'spi' to avoid namespace conflict
- use .one_transfer() callback instead of .one_message().
- drop /CS assert-deassert functions as core provides those.
- fix race while completing transfer before disabling interrupt.

 drivers/spi/Kconfig |6 +
 drivers/spi/Makefile|1 +
 drivers/spi/spi-pic32.c | 1004 +++
 3 files changed, 1011 insertions(+)
 create mode 100644 drivers/spi/spi-pic32.c

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 7706416..22f973f 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -396,6 +396,12 @@ config SPI_ORION
help
  This enables using the SPI master controller on the Orion chips.
 
+config SPI_PIC32
+   tristate "Microchip PIC32 series SPI"
+   depends on MACH_PIC32 || COMPILE_TEST
+   help
+ SPI driver for Microchip PIC32 SPI master controller.
+
 config SPI_PL022
tristate "ARM AMBA PL022 SSP controller"
depends on ARM_AMBA
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 8991ffc..1bcb417 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -60,6 +60,7 @@ obj-$(CONFIG_SPI_OMAP_100K)   += spi-omap-100k.o
 obj-$(CONFIG_SPI_OMAP24XX) += spi-omap2-mcspi.o
 obj-$(CONFIG_SPI_TI_QSPI)  += spi-ti-qspi.o
 obj-$(CONFIG_SPI_ORION)+= spi-orion.o
+obj-$(CONFIG_SPI_PIC32)+= spi-pic32.o
 obj-$(CONFIG_SPI_PL022)+= spi-pl022.o
 obj-$(CONFIG_SPI_PPC4xx)   += spi-ppc4xx.o
 spi-pxa2xx-platform-objs   := spi-pxa2xx.o
diff --git a/drivers/spi/spi-pic32.c b/drivers/spi/spi-pic32.c
new file mode 100644
index 000..8627aa1
--- /dev/null
+++ b/drivers/spi/spi-pic32.c
@@ -0,0 +1,1004 @@
+/*
+ * Microchip PIC32 SPI controller driver.
+ *
+ * Purna Chandra Mandal 
+ * Copyright (c) 2016, Microchip Technology Inc.
+ *
+ * This program is free software; you can distribute it and/or modify it
+ * under the terms of the GNU General Public License (Version 2) as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * for more details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* SPI Register offsets */
+struct pic32_spi_regs {
+   u32 ctrl;
+   u32 ctrl_clr;
+   u32 ctrl_set;
+   u32 ctrl_inv;
+   u32 status;
+   u32 status_clr;
+   u32 status_set;
+   u32 status_inv;
+   u32 buf;
+   u32 reserved[3];
+   u32 baud;
+   u32 reserved2[3];
+   u32 ctrl2;
+   u32 ctrl2_clr;
+   u32 ctrl2_set;
+   u32 ctrl2_inv;
+};
+
+/* Bit fields in SPI Control Register */
+#define CTRL_RX_INT_SHIFT  0  /* Rx interrupt generation */
+#define  RX_FIFO_EMTPY 0
+#define  RX_FIFO_NOT_EMPTY 1 /* not empty */
+#define  RX_FIFO_HALF_FULL 2 /* full by half or more */
+#define  RX_FIFO_FULL  3 /* completely full */
+
+#define CTRL_TX_INT_SHIFT  2  /* TX interrupt generation */
+#define  TX_FIFO_ALL_EMPTY 0 /* completely empty */
+#define  TX_FIFO_EMTPY 1 /* empty */
+#define  TX_FIFO_HALF_EMPTY2 /* empty by half or more */
+#define  TX_FIFO_NOT_FULL  3 /* atleast one empty */
+
+#define CTRL_MSTEN BIT(5) /* enable master mode */
+#define CTRL_CKP   BIT(6) /* active low */
+#define CTRL_CKE   BIT(8) /* Tx on falling edge */
+#define CTRL_SMP   BIT(9) /* Rx at middle or end of tx */
+#define CTRL_BPW_MASK  0x03   /* bits per word/sample */
+#define CTRL_BPW_SHIFT 10
+#define  PIC32_BPW_8   0
+#define  PIC32_BPW_16  1
+#define  PIC32_BPW_32  2
+#define CTRL_ONBIT(15) /* enable macro */
+#define CTRL_ENHBUFBIT(16) /* enable enhanced buffering */
+#define CTRL_MCLKSEL   BIT(23) /* select clock source */
+#define CTRL_MSSEN BIT(28) /* macro driven /SS */
+#define

[PATCH v2 2/2] spi: spi-pic32: Add PIC32 SPI master driver

2016-03-04 Thread Purna Chandra Mandal 
The PIC32 SPI driver is capable of performing SPI transfers
using PIO or external DMA engine. GPIO controlled /CS support
is made default in the driver for correct operation of the
controller. This can be enabled by adding "cs-gpios" property
of the SPI node in board dts file.

Signed-off-by: Purna Chandra Mandal 

---

Changes in v2:
- drop internal function drain_rx_fifo()
- merge wrapper functions with callers wherever applicable
- sort includes alphabetically
- Kconfig: sort SPI_PIC32 alphabetically and add || COMPILE_TEST
- Makefile: sort SPI_PIC32 alphabetically
- replace cpu_relax() with ndelay() in disable_chip()
- drop spi controller driven /CS management completely, use only
  GPIO controller /CS.
- rename function names starting with 'spi' to avoid namespace conflict
- use .one_transfer() callback instead of .one_message().
- drop /CS assert-deassert functions as core provides those.
- fix race while completing transfer before disabling interrupt.

 drivers/spi/Kconfig |6 +
 drivers/spi/Makefile|1 +
 drivers/spi/spi-pic32.c | 1004 +++
 3 files changed, 1011 insertions(+)
 create mode 100644 drivers/spi/spi-pic32.c

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 7706416..22f973f 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -396,6 +396,12 @@ config SPI_ORION
help
  This enables using the SPI master controller on the Orion chips.
 
+config SPI_PIC32
+   tristate "Microchip PIC32 series SPI"
+   depends on MACH_PIC32 || COMPILE_TEST
+   help
+ SPI driver for Microchip PIC32 SPI master controller.
+
 config SPI_PL022
tristate "ARM AMBA PL022 SSP controller"
depends on ARM_AMBA
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 8991ffc..1bcb417 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -60,6 +60,7 @@ obj-$(CONFIG_SPI_OMAP_100K)   += spi-omap-100k.o
 obj-$(CONFIG_SPI_OMAP24XX) += spi-omap2-mcspi.o
 obj-$(CONFIG_SPI_TI_QSPI)  += spi-ti-qspi.o
 obj-$(CONFIG_SPI_ORION)+= spi-orion.o
+obj-$(CONFIG_SPI_PIC32)+= spi-pic32.o
 obj-$(CONFIG_SPI_PL022)+= spi-pl022.o
 obj-$(CONFIG_SPI_PPC4xx)   += spi-ppc4xx.o
 spi-pxa2xx-platform-objs   := spi-pxa2xx.o
diff --git a/drivers/spi/spi-pic32.c b/drivers/spi/spi-pic32.c
new file mode 100644
index 000..8627aa1
--- /dev/null
+++ b/drivers/spi/spi-pic32.c
@@ -0,0 +1,1004 @@
+/*
+ * Microchip PIC32 SPI controller driver.
+ *
+ * Purna Chandra Mandal 
+ * Copyright (c) 2016, Microchip Technology Inc.
+ *
+ * This program is free software; you can distribute it and/or modify it
+ * under the terms of the GNU General Public License (Version 2) as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * for more details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* SPI Register offsets */
+struct pic32_spi_regs {
+   u32 ctrl;
+   u32 ctrl_clr;
+   u32 ctrl_set;
+   u32 ctrl_inv;
+   u32 status;
+   u32 status_clr;
+   u32 status_set;
+   u32 status_inv;
+   u32 buf;
+   u32 reserved[3];
+   u32 baud;
+   u32 reserved2[3];
+   u32 ctrl2;
+   u32 ctrl2_clr;
+   u32 ctrl2_set;
+   u32 ctrl2_inv;
+};
+
+/* Bit fields in SPI Control Register */
+#define CTRL_RX_INT_SHIFT  0  /* Rx interrupt generation */
+#define  RX_FIFO_EMTPY 0
+#define  RX_FIFO_NOT_EMPTY 1 /* not empty */
+#define  RX_FIFO_HALF_FULL 2 /* full by half or more */
+#define  RX_FIFO_FULL  3 /* completely full */
+
+#define CTRL_TX_INT_SHIFT  2  /* TX interrupt generation */
+#define  TX_FIFO_ALL_EMPTY 0 /* completely empty */
+#define  TX_FIFO_EMTPY 1 /* empty */
+#define  TX_FIFO_HALF_EMPTY2 /* empty by half or more */
+#define  TX_FIFO_NOT_FULL  3 /* atleast one empty */
+
+#define CTRL_MSTEN BIT(5) /* enable master mode */
+#define CTRL_CKP   BIT(6) /* active low */
+#define CTRL_CKE   BIT(8) /* Tx on falling edge */
+#define CTRL_SMP   BIT(9) /* Rx at middle or end of tx */
+#define CTRL_BPW_MASK  0x03   /* bits per word/sample */
+#define CTRL_BPW_SHIFT 10
+#define  PIC32_BPW_8   0
+#define  PIC32_BPW_16  1
+#define  PIC32_BPW_32  2
+#define CTRL_ONBIT(15) /* enable macro */
+#define CTRL_ENHBUFBIT(16) /* enable enhanced buffering */
+#define CTRL_MCLKSEL   BIT(23) /* select clock source */
+#define CTRL_MSSEN BIT(28) /* macro driven /SS */
+#define CTRL_FRMEN BIT(31) /* enable framing mode */
+
+/*