[PATCH v2 2/3] ASoC: stm32: Add I2S driver

2017-05-10 Thread olivier moysan 
Add I2S ASoC driver for STM32.
This version of the driver supports only
exclusive playback and capture interface.

Signed-off-by: olivier moysan 
---
 sound/soc/stm/Kconfig |   2 +-
 sound/soc/stm/Makefile|   4 +
 sound/soc/stm/stm32_i2s.c | 941 ++
 3 files changed, 946 insertions(+), 1 deletion(-)
 create mode 100644 sound/soc/stm/stm32_i2s.c

diff --git a/sound/soc/stm/Kconfig b/sound/soc/stm/Kconfig
index 972970f..a6372de 100644
--- a/sound/soc/stm/Kconfig
+++ b/sound/soc/stm/Kconfig
@@ -5,4 +5,4 @@ menuconfig SND_SOC_STM32
select SND_SOC_GENERIC_DMAENGINE_PCM
select REGMAP_MMIO
help
- Say Y if you want to enable ASoC-support for STM32
+ Say Y if you want to enable ASoC support for STM32
diff --git a/sound/soc/stm/Makefile b/sound/soc/stm/Makefile
index e466a47..8251931 100644
--- a/sound/soc/stm/Makefile
+++ b/sound/soc/stm/Makefile
@@ -4,3 +4,7 @@ obj-$(CONFIG_SND_SOC_STM32) += snd-soc-stm32-sai-sub.o
 
 snd-soc-stm32-sai-objs := stm32_sai.o
 obj-$(CONFIG_SND_SOC_STM32) += snd-soc-stm32-sai.o
+
+# I2S
+snd-soc-stm32-i2s-objs := stm32_i2s.o
+obj-$(CONFIG_SND_SOC_STM32) += snd-soc-stm32-i2s.o
diff --git a/sound/soc/stm/stm32_i2s.c b/sound/soc/stm/stm32_i2s.c
new file mode 100644
index 000..22152a1
--- /dev/null
+++ b/sound/soc/stm/stm32_i2s.c
@@ -0,0 +1,941 @@
+/*
+ *  STM32 ALSA SoC Digital Audio Interface (I2S) driver.
+ *
+ * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+ * Author(s): Olivier Moysan  for STMicroelectronics.
+ *
+ * License terms: GPL V2.0.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 
or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 
more
+ * details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+#define STM32_I2S_CR1_REG  0x0
+#define STM32_I2S_CFG1_REG 0x08
+#define STM32_I2S_CFG2_REG 0x0C
+#define STM32_I2S_IER_REG  0x10
+#define STM32_I2S_SR_REG   0x14
+#define STM32_I2S_IFCR_REG 0x18
+#define STM32_I2S_TXDR_REG 0X20
+#define STM32_I2S_RXDR_REG 0x30
+#define STM32_I2S_CGFR_REG 0X50
+
+/* Bit definition for SPI2S_CR1 register */
+#define I2S_CR1_SPEBIT(0)
+#define I2S_CR1_CSTART BIT(9)
+#define I2S_CR1_CSUSP  BIT(10)
+#define I2S_CR1_HDDIR  BIT(11)
+#define I2S_CR1_SSIBIT(12)
+#define I2S_CR1_CRC33_17   BIT(13)
+#define I2S_CR1_RCRCI  BIT(14)
+#define I2S_CR1_TCRCI  BIT(15)
+
+/* Bit definition for SPI_CFG2 register */
+#define I2S_CFG2_IOSWP_SHIFT   15
+#define I2S_CFG2_IOSWP BIT(I2S_CFG2_IOSWP_SHIFT)
+#define I2S_CFG2_LSBFRST   BIT(23)
+#define I2S_CFG2_AFCNTRBIT(31)
+
+/* Bit definition for SPI_CFG1 register */
+#define I2S_CFG1_FTHVL_SHIFT   5
+#define I2S_CFG1_FTHVL_MASKGENMASK(8, I2S_CFG1_FTHVL_SHIFT)
+#define I2S_CFG1_FTHVL_SET(x)  ((x) << I2S_CFG1_FTHVL_SHIFT)
+
+#define I2S_CFG1_TXDMAEN   BIT(15)
+#define I2S_CFG1_RXDMAEN   BIT(14)
+
+/* Bit definition for SPI2S_IER register */
+#define I2S_IER_RXPIE  BIT(0)
+#define I2S_IER_TXPIE  BIT(1)
+#define I2S_IER_DPXPIE BIT(2)
+#define I2S_IER_EOTIE  BIT(3)
+#define I2S_IER_TXTFIE BIT(4)
+#define I2S_IER_UDRIE  BIT(5)
+#define I2S_IER_OVRIE  BIT(6)
+#define I2S_IER_CRCEIE BIT(7)
+#define I2S_IER_TIFREIEBIT(8)
+#define I2S_IER_MODFIE BIT(9)
+#define I2S_IER_TSERFIEBIT(10)
+
+/* Bit definition for SPI2S_SR register */
+#define I2S_SR_RXP BIT(0)
+#define I2S_SR_TXP BIT(1)
+#define I2S_SR_DPXPBIT(2)
+#define I2S_SR_EOT BIT(3)
+#define I2S_SR_TXTFBIT(4)
+#define I2S_SR_UDR BIT(5)
+#define I2S_SR_OVR BIT(6)
+#define I2S_SR_CRCERR  BIT(7)
+#define I2S_SR_TIFRE   BIT(8)
+#define I2S_SR_MODFBIT(9)
+#define I2S_SR_TSERF   BIT(10)
+#define I2S_SR_SUSPBIT(11)
+#define I2S_SR_TXC BIT(12)
+#define I2S_SR_RXPLVL  GENMASK(14, 13)
+#define I2S_SR_RXWNE   BIT(15)
+
+#define I2S_SR_MASKGENMASK(15, 0)
+
+/* Bit definition for SPI_IFCR register */
+#define I2S_IFCR_EOTC  BIT(3)
+#define I2S_IFCR_TXTFC BIT(4)
+#define I2S_IFCR_UDRC  BIT(5)
+#define I2S_IFCR_OVRC  BIT(6)
+#define I2S_IFCR_CRCEC BIT(7)
+#define I2S_IFCR_TIFRECBIT(8)
+#define I2S_IFCR_MODFC BIT(9)
+#define I2S_IFCR_TSERFCBIT(10)
+#define

[PATCH v2 2/3] ASoC: stm32: Add I2S driver

2017-05-10 Thread olivier moysan 
Add I2S ASoC driver for STM32.
This version of the driver supports only
exclusive playback and capture interface.

Signed-off-by: olivier moysan 
---
 sound/soc/stm/Kconfig |   2 +-
 sound/soc/stm/Makefile|   4 +
 sound/soc/stm/stm32_i2s.c | 941 ++
 3 files changed, 946 insertions(+), 1 deletion(-)
 create mode 100644 sound/soc/stm/stm32_i2s.c

diff --git a/sound/soc/stm/Kconfig b/sound/soc/stm/Kconfig
index 972970f..a6372de 100644
--- a/sound/soc/stm/Kconfig
+++ b/sound/soc/stm/Kconfig
@@ -5,4 +5,4 @@ menuconfig SND_SOC_STM32
select SND_SOC_GENERIC_DMAENGINE_PCM
select REGMAP_MMIO
help
- Say Y if you want to enable ASoC-support for STM32
+ Say Y if you want to enable ASoC support for STM32
diff --git a/sound/soc/stm/Makefile b/sound/soc/stm/Makefile
index e466a47..8251931 100644
--- a/sound/soc/stm/Makefile
+++ b/sound/soc/stm/Makefile
@@ -4,3 +4,7 @@ obj-$(CONFIG_SND_SOC_STM32) += snd-soc-stm32-sai-sub.o
 
 snd-soc-stm32-sai-objs := stm32_sai.o
 obj-$(CONFIG_SND_SOC_STM32) += snd-soc-stm32-sai.o
+
+# I2S
+snd-soc-stm32-i2s-objs := stm32_i2s.o
+obj-$(CONFIG_SND_SOC_STM32) += snd-soc-stm32-i2s.o
diff --git a/sound/soc/stm/stm32_i2s.c b/sound/soc/stm/stm32_i2s.c
new file mode 100644
index 000..22152a1
--- /dev/null
+++ b/sound/soc/stm/stm32_i2s.c
@@ -0,0 +1,941 @@
+/*
+ *  STM32 ALSA SoC Digital Audio Interface (I2S) driver.
+ *
+ * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+ * Author(s): Olivier Moysan  for STMicroelectronics.
+ *
+ * License terms: GPL V2.0.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 
or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 
more
+ * details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+#define STM32_I2S_CR1_REG  0x0
+#define STM32_I2S_CFG1_REG 0x08
+#define STM32_I2S_CFG2_REG 0x0C
+#define STM32_I2S_IER_REG  0x10
+#define STM32_I2S_SR_REG   0x14
+#define STM32_I2S_IFCR_REG 0x18
+#define STM32_I2S_TXDR_REG 0X20
+#define STM32_I2S_RXDR_REG 0x30
+#define STM32_I2S_CGFR_REG 0X50
+
+/* Bit definition for SPI2S_CR1 register */
+#define I2S_CR1_SPEBIT(0)
+#define I2S_CR1_CSTART BIT(9)
+#define I2S_CR1_CSUSP  BIT(10)
+#define I2S_CR1_HDDIR  BIT(11)
+#define I2S_CR1_SSIBIT(12)
+#define I2S_CR1_CRC33_17   BIT(13)
+#define I2S_CR1_RCRCI  BIT(14)
+#define I2S_CR1_TCRCI  BIT(15)
+
+/* Bit definition for SPI_CFG2 register */
+#define I2S_CFG2_IOSWP_SHIFT   15
+#define I2S_CFG2_IOSWP BIT(I2S_CFG2_IOSWP_SHIFT)
+#define I2S_CFG2_LSBFRST   BIT(23)
+#define I2S_CFG2_AFCNTRBIT(31)
+
+/* Bit definition for SPI_CFG1 register */
+#define I2S_CFG1_FTHVL_SHIFT   5
+#define I2S_CFG1_FTHVL_MASKGENMASK(8, I2S_CFG1_FTHVL_SHIFT)
+#define I2S_CFG1_FTHVL_SET(x)  ((x) << I2S_CFG1_FTHVL_SHIFT)
+
+#define I2S_CFG1_TXDMAEN   BIT(15)
+#define I2S_CFG1_RXDMAEN   BIT(14)
+
+/* Bit definition for SPI2S_IER register */
+#define I2S_IER_RXPIE  BIT(0)
+#define I2S_IER_TXPIE  BIT(1)
+#define I2S_IER_DPXPIE BIT(2)
+#define I2S_IER_EOTIE  BIT(3)
+#define I2S_IER_TXTFIE BIT(4)
+#define I2S_IER_UDRIE  BIT(5)
+#define I2S_IER_OVRIE  BIT(6)
+#define I2S_IER_CRCEIE BIT(7)
+#define I2S_IER_TIFREIEBIT(8)
+#define I2S_IER_MODFIE BIT(9)
+#define I2S_IER_TSERFIEBIT(10)
+
+/* Bit definition for SPI2S_SR register */
+#define I2S_SR_RXP BIT(0)
+#define I2S_SR_TXP BIT(1)
+#define I2S_SR_DPXPBIT(2)
+#define I2S_SR_EOT BIT(3)
+#define I2S_SR_TXTFBIT(4)
+#define I2S_SR_UDR BIT(5)
+#define I2S_SR_OVR BIT(6)
+#define I2S_SR_CRCERR  BIT(7)
+#define I2S_SR_TIFRE   BIT(8)
+#define I2S_SR_MODFBIT(9)
+#define I2S_SR_TSERF   BIT(10)
+#define I2S_SR_SUSPBIT(11)
+#define I2S_SR_TXC BIT(12)
+#define I2S_SR_RXPLVL  GENMASK(14, 13)
+#define I2S_SR_RXWNE   BIT(15)
+
+#define I2S_SR_MASKGENMASK(15, 0)
+
+/* Bit definition for SPI_IFCR register */
+#define I2S_IFCR_EOTC  BIT(3)
+#define I2S_IFCR_TXTFC BIT(4)
+#define I2S_IFCR_UDRC  BIT(5)
+#define I2S_IFCR_OVRC  BIT(6)
+#define I2S_IFCR_CRCEC BIT(7)
+#define I2S_IFCR_TIFRECBIT(8)
+#define I2S_IFCR_MODFC BIT(9)
+#define I2S_IFCR_TSERFCBIT(10)
+#define I2S_IFCR_SUSPC BIT(11)
+
+#define