Re: [PATCH v2 2/3] clk: meson-gxbb: Add MALI clocks

2017-03-02 Thread Jerome Brunet 
On Thu, 2017-03-02 at 12:07 +0100, Neil Armstrong wrote:
> Hi Stephen,
> 
> On 03/01/2017 08:11 PM, Stephen Boyd wrote:
> > On 03/01, Neil Armstrong wrote:
> > > diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
> > > index a52063f..31f6090 100644
> > > --- a/drivers/clk/meson/gxbb.c
> > > +++ b/drivers/clk/meson/gxbb.c
> > > @@ -634,6 +634,131 @@
> > >   },
> > >  };
> > >  
> > > +/*
> > > + * The MALI IP is clocked by two identical clocks (mali_0 and
> > > mali_1)
> > > + * muxed by a glitch-free switch.
> > > + */
> > > +
> > > +static u32 mux_table_mali_0_1[] = {0, 1, 2, 3, 4, 5, 6, 7};
> > > +const char *gxbb_mali_0_1_parent_names[] = {
> > 
> > static?
> 
> Will do !
> 
> > 
> > > + "xtal", "gp0_pll", "mpll2", "mpll1", "fclk_div7",
> > > + "fclk_div4", "fclk_div3", "fclk_div5"
> > > +};
> > > +
> > 
> > [..]
> > > + .reg = (void *)HHI_MALI_CLK_CNTL,
> > > + .bit_idx = 24,
> > > + .lock = _lock,
> > > + .hw.init = &(struct clk_init_data){
> > > + .name = "mali_1",
> > > + .ops = _gate_ops,
> > > + .parent_names = (const char *[]){ "mali_1_div"
> > > },
> > > + .num_parents = 1,
> > > + .flags = (CLK_SET_RATE_PARENT |
> > > CLK_IGNORE_UNUSED),
> > > + },
> > > +};
> > > +
> > > +static u32 mux_table_mali[] = {0, 1};
> > > +const char *gxbb_mali_parent_names[] = {
> > 
> > static?
> > 
> > > + "mali_0", "mali_1"
> > > +};
> > 
> > [...]
> > >  static struct clk_mux *gxbb_clk_muxes[] = {
> > >   _mpeg_clk_sel,
> > >   _sar_adc_clk_sel,
> > > + _mali_0_sel,
> > > + _mali_1_sel,
> > > + _mali,
> > >  };
> > >  
> > >  static struct clk_divider *gxbb_clk_dividers[] = {
> > 
> > Can these arrays be const? If so, please do that in a separate
> > patch.
> 
> Hmm, these were introduced by jerome, he should update them
> accordingly.
> 

Will do

> > >   _mpeg_clk_div,
> > >   _sar_adc_clk_div,
> > > + _mali_0_div,
> > > + _mali_1_div,
> > >  };
> 
> 
> Thanks,
> Neil

Re: [PATCH v2 2/3] clk: meson-gxbb: Add MALI clocks

2017-03-02 Thread Jerome Brunet 
On Thu, 2017-03-02 at 12:07 +0100, Neil Armstrong wrote:
> Hi Stephen,
> 
> On 03/01/2017 08:11 PM, Stephen Boyd wrote:
> > On 03/01, Neil Armstrong wrote:
> > > diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
> > > index a52063f..31f6090 100644
> > > --- a/drivers/clk/meson/gxbb.c
> > > +++ b/drivers/clk/meson/gxbb.c
> > > @@ -634,6 +634,131 @@
> > >   },
> > >  };
> > >  
> > > +/*
> > > + * The MALI IP is clocked by two identical clocks (mali_0 and
> > > mali_1)
> > > + * muxed by a glitch-free switch.
> > > + */
> > > +
> > > +static u32 mux_table_mali_0_1[] = {0, 1, 2, 3, 4, 5, 6, 7};
> > > +const char *gxbb_mali_0_1_parent_names[] = {
> > 
> > static?
> 
> Will do !
> 
> > 
> > > + "xtal", "gp0_pll", "mpll2", "mpll1", "fclk_div7",
> > > + "fclk_div4", "fclk_div3", "fclk_div5"
> > > +};
> > > +
> > 
> > [..]
> > > + .reg = (void *)HHI_MALI_CLK_CNTL,
> > > + .bit_idx = 24,
> > > + .lock = _lock,
> > > + .hw.init = &(struct clk_init_data){
> > > + .name = "mali_1",
> > > + .ops = _gate_ops,
> > > + .parent_names = (const char *[]){ "mali_1_div"
> > > },
> > > + .num_parents = 1,
> > > + .flags = (CLK_SET_RATE_PARENT |
> > > CLK_IGNORE_UNUSED),
> > > + },
> > > +};
> > > +
> > > +static u32 mux_table_mali[] = {0, 1};
> > > +const char *gxbb_mali_parent_names[] = {
> > 
> > static?
> > 
> > > + "mali_0", "mali_1"
> > > +};
> > 
> > [...]
> > >  static struct clk_mux *gxbb_clk_muxes[] = {
> > >   _mpeg_clk_sel,
> > >   _sar_adc_clk_sel,
> > > + _mali_0_sel,
> > > + _mali_1_sel,
> > > + _mali,
> > >  };
> > >  
> > >  static struct clk_divider *gxbb_clk_dividers[] = {
> > 
> > Can these arrays be const? If so, please do that in a separate
> > patch.
> 
> Hmm, these were introduced by jerome, he should update them
> accordingly.
> 

Will do

> > >   _mpeg_clk_div,
> > >   _sar_adc_clk_div,
> > > + _mali_0_div,
> > > + _mali_1_div,
> > >  };
> 
> 
> Thanks,
> Neil

Re: [PATCH v2 2/3] clk: meson-gxbb: Add MALI clocks

2017-03-02 Thread Neil Armstrong 
Hi Stephen,

On 03/01/2017 08:11 PM, Stephen Boyd wrote:
> On 03/01, Neil Armstrong wrote:
>> diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
>> index a52063f..31f6090 100644
>> --- a/drivers/clk/meson/gxbb.c
>> +++ b/drivers/clk/meson/gxbb.c
>> @@ -634,6 +634,131 @@
>>  },
>>  };
>>  
>> +/*
>> + * The MALI IP is clocked by two identical clocks (mali_0 and mali_1)
>> + * muxed by a glitch-free switch.
>> + */
>> +
>> +static u32 mux_table_mali_0_1[] = {0, 1, 2, 3, 4, 5, 6, 7};
>> +const char *gxbb_mali_0_1_parent_names[] = {
> 
> static?

Will do !

> 
>> +"xtal", "gp0_pll", "mpll2", "mpll1", "fclk_div7",
>> +"fclk_div4", "fclk_div3", "fclk_div5"
>> +};
>> +
> [..]
>> +.reg = (void *)HHI_MALI_CLK_CNTL,
>> +.bit_idx = 24,
>> +.lock = _lock,
>> +.hw.init = &(struct clk_init_data){
>> +.name = "mali_1",
>> +.ops = _gate_ops,
>> +.parent_names = (const char *[]){ "mali_1_div" },
>> +.num_parents = 1,
>> +.flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED),
>> +},
>> +};
>> +
>> +static u32 mux_table_mali[] = {0, 1};
>> +const char *gxbb_mali_parent_names[] = {
> 
> static?
> 
>> +"mali_0", "mali_1"
>> +};
> [...]
>>  static struct clk_mux *gxbb_clk_muxes[] = {
>>  _mpeg_clk_sel,
>>  _sar_adc_clk_sel,
>> +_mali_0_sel,
>> +_mali_1_sel,
>> +_mali,
>>  };
>>  
>>  static struct clk_divider *gxbb_clk_dividers[] = {
> 
> Can these arrays be const? If so, please do that in a separate
> patch.

Hmm, these were introduced by jerome, he should update them accordingly.

>>  _mpeg_clk_div,
>>  _sar_adc_clk_div,
>> +_mali_0_div,
>> +_mali_1_div,
>>  };


Thanks,
Neil

Re: [PATCH v2 2/3] clk: meson-gxbb: Add MALI clocks

2017-03-02 Thread Neil Armstrong 
Hi Stephen,

On 03/01/2017 08:11 PM, Stephen Boyd wrote:
> On 03/01, Neil Armstrong wrote:
>> diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
>> index a52063f..31f6090 100644
>> --- a/drivers/clk/meson/gxbb.c
>> +++ b/drivers/clk/meson/gxbb.c
>> @@ -634,6 +634,131 @@
>>  },
>>  };
>>  
>> +/*
>> + * The MALI IP is clocked by two identical clocks (mali_0 and mali_1)
>> + * muxed by a glitch-free switch.
>> + */
>> +
>> +static u32 mux_table_mali_0_1[] = {0, 1, 2, 3, 4, 5, 6, 7};
>> +const char *gxbb_mali_0_1_parent_names[] = {
> 
> static?

Will do !

> 
>> +"xtal", "gp0_pll", "mpll2", "mpll1", "fclk_div7",
>> +"fclk_div4", "fclk_div3", "fclk_div5"
>> +};
>> +
> [..]
>> +.reg = (void *)HHI_MALI_CLK_CNTL,
>> +.bit_idx = 24,
>> +.lock = _lock,
>> +.hw.init = &(struct clk_init_data){
>> +.name = "mali_1",
>> +.ops = _gate_ops,
>> +.parent_names = (const char *[]){ "mali_1_div" },
>> +.num_parents = 1,
>> +.flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED),
>> +},
>> +};
>> +
>> +static u32 mux_table_mali[] = {0, 1};
>> +const char *gxbb_mali_parent_names[] = {
> 
> static?
> 
>> +"mali_0", "mali_1"
>> +};
> [...]
>>  static struct clk_mux *gxbb_clk_muxes[] = {
>>  _mpeg_clk_sel,
>>  _sar_adc_clk_sel,
>> +_mali_0_sel,
>> +_mali_1_sel,
>> +_mali,
>>  };
>>  
>>  static struct clk_divider *gxbb_clk_dividers[] = {
> 
> Can these arrays be const? If so, please do that in a separate
> patch.

Hmm, these were introduced by jerome, he should update them accordingly.

>>  _mpeg_clk_div,
>>  _sar_adc_clk_div,
>> +_mali_0_div,
>> +_mali_1_div,
>>  };


Thanks,
Neil

Re: [PATCH v2 2/3] clk: meson-gxbb: Add MALI clocks

2017-03-01 Thread Stephen Boyd 
On 03/01, Neil Armstrong wrote:
> diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
> index a52063f..31f6090 100644
> --- a/drivers/clk/meson/gxbb.c
> +++ b/drivers/clk/meson/gxbb.c
> @@ -634,6 +634,131 @@
>   },
>  };
>  
> +/*
> + * The MALI IP is clocked by two identical clocks (mali_0 and mali_1)
> + * muxed by a glitch-free switch.
> + */
> +
> +static u32 mux_table_mali_0_1[] = {0, 1, 2, 3, 4, 5, 6, 7};
> +const char *gxbb_mali_0_1_parent_names[] = {

static?

> + "xtal", "gp0_pll", "mpll2", "mpll1", "fclk_div7",
> + "fclk_div4", "fclk_div3", "fclk_div5"
> +};
> +
[..]
> + .reg = (void *)HHI_MALI_CLK_CNTL,
> + .bit_idx = 24,
> + .lock = _lock,
> + .hw.init = &(struct clk_init_data){
> + .name = "mali_1",
> + .ops = _gate_ops,
> + .parent_names = (const char *[]){ "mali_1_div" },
> + .num_parents = 1,
> + .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED),
> + },
> +};
> +
> +static u32 mux_table_mali[] = {0, 1};
> +const char *gxbb_mali_parent_names[] = {

static?

> + "mali_0", "mali_1"
> +};
[...]
>  static struct clk_mux *gxbb_clk_muxes[] = {
>   _mpeg_clk_sel,
>   _sar_adc_clk_sel,
> + _mali_0_sel,
> + _mali_1_sel,
> + _mali,
>  };
>  
>  static struct clk_divider *gxbb_clk_dividers[] = {

Can these arrays be const? If so, please do that in a separate
patch.

>   _mpeg_clk_div,
>   _sar_adc_clk_div,
> + _mali_0_div,
> + _mali_1_div,
>  };
-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH v2 2/3] clk: meson-gxbb: Add MALI clocks

2017-03-01 Thread Stephen Boyd 
On 03/01, Neil Armstrong wrote:
> diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
> index a52063f..31f6090 100644
> --- a/drivers/clk/meson/gxbb.c
> +++ b/drivers/clk/meson/gxbb.c
> @@ -634,6 +634,131 @@
>   },
>  };
>  
> +/*
> + * The MALI IP is clocked by two identical clocks (mali_0 and mali_1)
> + * muxed by a glitch-free switch.
> + */
> +
> +static u32 mux_table_mali_0_1[] = {0, 1, 2, 3, 4, 5, 6, 7};
> +const char *gxbb_mali_0_1_parent_names[] = {

static?

> + "xtal", "gp0_pll", "mpll2", "mpll1", "fclk_div7",
> + "fclk_div4", "fclk_div3", "fclk_div5"
> +};
> +
[..]
> + .reg = (void *)HHI_MALI_CLK_CNTL,
> + .bit_idx = 24,
> + .lock = _lock,
> + .hw.init = &(struct clk_init_data){
> + .name = "mali_1",
> + .ops = _gate_ops,
> + .parent_names = (const char *[]){ "mali_1_div" },
> + .num_parents = 1,
> + .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED),
> + },
> +};
> +
> +static u32 mux_table_mali[] = {0, 1};
> +const char *gxbb_mali_parent_names[] = {

static?

> + "mali_0", "mali_1"
> +};
[...]
>  static struct clk_mux *gxbb_clk_muxes[] = {
>   _mpeg_clk_sel,
>   _sar_adc_clk_sel,
> + _mali_0_sel,
> + _mali_1_sel,
> + _mali,
>  };
>  
>  static struct clk_divider *gxbb_clk_dividers[] = {

Can these arrays be const? If so, please do that in a separate
patch.

>   _mpeg_clk_div,
>   _sar_adc_clk_div,
> + _mali_0_div,
> + _mali_1_div,
>  };
-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH v2 2/3] clk: meson-gxbb: Add MALI clocks

2017-03-01 Thread Neil Armstrong 
The Mali is clocked by two identical clock paths behind a glitch free mux
to safely change frequency while running.

The two "mali_0" and "mali_1" clocks are composed of a mux, divider and gate.
Expose these two clocks trees using generic clocks.
Finally the glitch free mux is added as "mali" clock.

Signed-off-by: Neil Armstrong 
---
 drivers/clk/meson/gxbb.c | 139 +++
 1 file changed, 139 insertions(+)

diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index a52063f..31f6090 100644
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -634,6 +634,131 @@
},
 };
 
+/*
+ * The MALI IP is clocked by two identical clocks (mali_0 and mali_1)
+ * muxed by a glitch-free switch.
+ */
+
+static u32 mux_table_mali_0_1[] = {0, 1, 2, 3, 4, 5, 6, 7};
+const char *gxbb_mali_0_1_parent_names[] = {
+   "xtal", "gp0_pll", "mpll2", "mpll1", "fclk_div7",
+   "fclk_div4", "fclk_div3", "fclk_div5"
+};
+
+static struct clk_mux gxbb_mali_0_sel = {
+   .reg = (void *)HHI_MALI_CLK_CNTL,
+   .mask = 0x7,
+   .shift = 9,
+   .table = mux_table_mali_0_1,
+   .lock = _lock,
+   .hw.init = &(struct clk_init_data){
+   .name = "mali_0_sel",
+   .ops = _mux_ops,
+   /*
+* bits 10:9 selects from 8 possible parents:
+* xtal, gp0_pll, mpll2, mpll1, fclk_div7,
+* fclk_div4, fclk_div3, fclk_div5
+*/
+   .parent_names = gxbb_mali_0_1_parent_names,
+   .num_parents = 8,
+   .flags = (CLK_SET_RATE_NO_REPARENT | CLK_IGNORE_UNUSED),
+   },
+};
+
+static struct clk_divider gxbb_mali_0_div = {
+   .reg = (void *)HHI_MALI_CLK_CNTL,
+   .shift = 0,
+   .width = 7,
+   .lock = _lock,
+   .hw.init = &(struct clk_init_data){
+   .name = "mali_0_div",
+   .ops = _divider_ops,
+   .parent_names = (const char *[]){ "mali_0_sel" },
+   .num_parents = 1,
+   .flags = (CLK_SET_RATE_NO_REPARENT | CLK_IGNORE_UNUSED),
+   },
+};
+
+static struct clk_gate gxbb_mali_0 = {
+   .reg = (void *)HHI_MALI_CLK_CNTL,
+   .bit_idx = 8,
+   .lock = _lock,
+   .hw.init = &(struct clk_init_data){
+   .name = "mali_0",
+   .ops = _gate_ops,
+   .parent_names = (const char *[]){ "mali_0_div" },
+   .num_parents = 1,
+   .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED),
+   },
+};
+
+static struct clk_mux gxbb_mali_1_sel = {
+   .reg = (void *)HHI_MALI_CLK_CNTL,
+   .mask = 0x7,
+   .shift = 25,
+   .table = mux_table_mali_0_1,
+   .lock = _lock,
+   .hw.init = &(struct clk_init_data){
+   .name = "mali_1_sel",
+   .ops = _mux_ops,
+   /*
+* bits 10:9 selects from 8 possible parents:
+* xtal, gp0_pll, mpll2, mpll1, fclk_div7,
+* fclk_div4, fclk_div3, fclk_div5
+*/
+   .parent_names = gxbb_mali_0_1_parent_names,
+   .num_parents = 8,
+   .flags = (CLK_SET_RATE_NO_REPARENT | CLK_IGNORE_UNUSED),
+   },
+};
+
+static struct clk_divider gxbb_mali_1_div = {
+   .reg = (void *)HHI_MALI_CLK_CNTL,
+   .shift = 16,
+   .width = 7,
+   .lock = _lock,
+   .hw.init = &(struct clk_init_data){
+   .name = "mali_1_div",
+   .ops = _divider_ops,
+   .parent_names = (const char *[]){ "mali_1_sel" },
+   .num_parents = 1,
+   .flags = (CLK_SET_RATE_NO_REPARENT | CLK_IGNORE_UNUSED),
+   },
+};
+
+static struct clk_gate gxbb_mali_1 = {
+   .reg = (void *)HHI_MALI_CLK_CNTL,
+   .bit_idx = 24,
+   .lock = _lock,
+   .hw.init = &(struct clk_init_data){
+   .name = "mali_1",
+   .ops = _gate_ops,
+   .parent_names = (const char *[]){ "mali_1_div" },
+   .num_parents = 1,
+   .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED),
+   },
+};
+
+static u32 mux_table_mali[] = {0, 1};
+const char *gxbb_mali_parent_names[] = {
+   "mali_0", "mali_1"
+};
+
+static struct clk_mux gxbb_mali = {
+   .reg = (void *)HHI_MALI_CLK_CNTL,
+   .mask = 1,
+   .shift = 31,
+   .table = mux_table_mali,
+   .lock = _lock,
+   .hw.init = &(struct clk_init_data){
+   .name = "mali",
+   .ops = _mux_ops,
+   .parent_names = gxbb_mali_parent_names,
+   .num_parents = 2,
+   .flags = (CLK_SET_RATE_NO_REPARENT | CLK_IGNORE_UNUSED),
+   },
+};
+
 /* Everything Else (EE) domain gates */
 static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
 static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);
@@ -827,6 +952,13 @@
[CLKID_SAR_ADC_CLK] = _sar_adc_clk.hw,

[PATCH v2 2/3] clk: meson-gxbb: Add MALI clocks

2017-03-01 Thread Neil Armstrong 
The Mali is clocked by two identical clock paths behind a glitch free mux
to safely change frequency while running.

The two "mali_0" and "mali_1" clocks are composed of a mux, divider and gate.
Expose these two clocks trees using generic clocks.
Finally the glitch free mux is added as "mali" clock.

Signed-off-by: Neil Armstrong 
---
 drivers/clk/meson/gxbb.c | 139 +++
 1 file changed, 139 insertions(+)

diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index a52063f..31f6090 100644
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -634,6 +634,131 @@
},
 };
 
+/*
+ * The MALI IP is clocked by two identical clocks (mali_0 and mali_1)
+ * muxed by a glitch-free switch.
+ */
+
+static u32 mux_table_mali_0_1[] = {0, 1, 2, 3, 4, 5, 6, 7};
+const char *gxbb_mali_0_1_parent_names[] = {
+   "xtal", "gp0_pll", "mpll2", "mpll1", "fclk_div7",
+   "fclk_div4", "fclk_div3", "fclk_div5"
+};
+
+static struct clk_mux gxbb_mali_0_sel = {
+   .reg = (void *)HHI_MALI_CLK_CNTL,
+   .mask = 0x7,
+   .shift = 9,
+   .table = mux_table_mali_0_1,
+   .lock = _lock,
+   .hw.init = &(struct clk_init_data){
+   .name = "mali_0_sel",
+   .ops = _mux_ops,
+   /*
+* bits 10:9 selects from 8 possible parents:
+* xtal, gp0_pll, mpll2, mpll1, fclk_div7,
+* fclk_div4, fclk_div3, fclk_div5
+*/
+   .parent_names = gxbb_mali_0_1_parent_names,
+   .num_parents = 8,
+   .flags = (CLK_SET_RATE_NO_REPARENT | CLK_IGNORE_UNUSED),
+   },
+};
+
+static struct clk_divider gxbb_mali_0_div = {
+   .reg = (void *)HHI_MALI_CLK_CNTL,
+   .shift = 0,
+   .width = 7,
+   .lock = _lock,
+   .hw.init = &(struct clk_init_data){
+   .name = "mali_0_div",
+   .ops = _divider_ops,
+   .parent_names = (const char *[]){ "mali_0_sel" },
+   .num_parents = 1,
+   .flags = (CLK_SET_RATE_NO_REPARENT | CLK_IGNORE_UNUSED),
+   },
+};
+
+static struct clk_gate gxbb_mali_0 = {
+   .reg = (void *)HHI_MALI_CLK_CNTL,
+   .bit_idx = 8,
+   .lock = _lock,
+   .hw.init = &(struct clk_init_data){
+   .name = "mali_0",
+   .ops = _gate_ops,
+   .parent_names = (const char *[]){ "mali_0_div" },
+   .num_parents = 1,
+   .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED),
+   },
+};
+
+static struct clk_mux gxbb_mali_1_sel = {
+   .reg = (void *)HHI_MALI_CLK_CNTL,
+   .mask = 0x7,
+   .shift = 25,
+   .table = mux_table_mali_0_1,
+   .lock = _lock,
+   .hw.init = &(struct clk_init_data){
+   .name = "mali_1_sel",
+   .ops = _mux_ops,
+   /*
+* bits 10:9 selects from 8 possible parents:
+* xtal, gp0_pll, mpll2, mpll1, fclk_div7,
+* fclk_div4, fclk_div3, fclk_div5
+*/
+   .parent_names = gxbb_mali_0_1_parent_names,
+   .num_parents = 8,
+   .flags = (CLK_SET_RATE_NO_REPARENT | CLK_IGNORE_UNUSED),
+   },
+};
+
+static struct clk_divider gxbb_mali_1_div = {
+   .reg = (void *)HHI_MALI_CLK_CNTL,
+   .shift = 16,
+   .width = 7,
+   .lock = _lock,
+   .hw.init = &(struct clk_init_data){
+   .name = "mali_1_div",
+   .ops = _divider_ops,
+   .parent_names = (const char *[]){ "mali_1_sel" },
+   .num_parents = 1,
+   .flags = (CLK_SET_RATE_NO_REPARENT | CLK_IGNORE_UNUSED),
+   },
+};
+
+static struct clk_gate gxbb_mali_1 = {
+   .reg = (void *)HHI_MALI_CLK_CNTL,
+   .bit_idx = 24,
+   .lock = _lock,
+   .hw.init = &(struct clk_init_data){
+   .name = "mali_1",
+   .ops = _gate_ops,
+   .parent_names = (const char *[]){ "mali_1_div" },
+   .num_parents = 1,
+   .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED),
+   },
+};
+
+static u32 mux_table_mali[] = {0, 1};
+const char *gxbb_mali_parent_names[] = {
+   "mali_0", "mali_1"
+};
+
+static struct clk_mux gxbb_mali = {
+   .reg = (void *)HHI_MALI_CLK_CNTL,
+   .mask = 1,
+   .shift = 31,
+   .table = mux_table_mali,
+   .lock = _lock,
+   .hw.init = &(struct clk_init_data){
+   .name = "mali",
+   .ops = _mux_ops,
+   .parent_names = gxbb_mali_parent_names,
+   .num_parents = 2,
+   .flags = (CLK_SET_RATE_NO_REPARENT | CLK_IGNORE_UNUSED),
+   },
+};
+
 /* Everything Else (EE) domain gates */
 static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
 static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);
@@ -827,6 +952,13 @@
[CLKID_SAR_ADC_CLK] = _sar_adc_clk.hw,
[CLKID_SAR_ADC_SEL] =