[PATCH v2 2/3] drm/radeon: Cleanup HDMI audio interrupt handling for evergreen

2017-05-19 Thread Lyude 
Same as the previous patch, but now for handling HDMI audio interrupts.

Changes since v1:
- Preserve the order we write back all registers

Signed-off-by: Lyude 
---
 drivers/gpu/drm/radeon/evergreen.c | 153 +++--
 drivers/gpu/drm/radeon/radeon.h|   7 +-
 2 files changed, 27 insertions(+), 133 deletions(-)

diff --git a/drivers/gpu/drm/radeon/evergreen.c 
b/drivers/gpu/drm/radeon/evergreen.c
index 44ac6d3..507a773 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -4495,7 +4495,6 @@ int evergreen_irq_set(struct radeon_device *rdev)
u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
u32 cp_int_cntl1 = 0, cp_int_cntl2 = 0;
u32 grbm_int_cntl = 0;
-   u32 afmt1 = 0, afmt2 = 0, afmt3 = 0, afmt4 = 0, afmt5 = 0, afmt6 = 0;
u32 dma_cntl, dma_cntl1 = 0;
u32 thermal_int = 0;
 
@@ -4518,13 +4517,6 @@ int evergreen_irq_set(struct radeon_device *rdev)
thermal_int = RREG32(CG_THERMAL_INT) &
~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
 
-   afmt1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + 
EVERGREEN_CRTC0_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
-   afmt2 = RREG32(AFMT_AUDIO_PACKET_CONTROL + 
EVERGREEN_CRTC1_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
-   afmt3 = RREG32(AFMT_AUDIO_PACKET_CONTROL + 
EVERGREEN_CRTC2_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
-   afmt4 = RREG32(AFMT_AUDIO_PACKET_CONTROL + 
EVERGREEN_CRTC3_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
-   afmt5 = RREG32(AFMT_AUDIO_PACKET_CONTROL + 
EVERGREEN_CRTC4_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
-   afmt6 = RREG32(AFMT_AUDIO_PACKET_CONTROL + 
EVERGREEN_CRTC5_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
-
dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
 
if (rdev->family >= CHIP_CAYMAN) {
@@ -4567,31 +4559,6 @@ int evergreen_irq_set(struct radeon_device *rdev)
thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
}
 
-   if (rdev->irq.afmt[0]) {
-   DRM_DEBUG("evergreen_irq_set: hdmi 0\n");
-   afmt1 |= AFMT_AZ_FORMAT_WTRIG_MASK;
-   }
-   if (rdev->irq.afmt[1]) {
-   DRM_DEBUG("evergreen_irq_set: hdmi 1\n");
-   afmt2 |= AFMT_AZ_FORMAT_WTRIG_MASK;
-   }
-   if (rdev->irq.afmt[2]) {
-   DRM_DEBUG("evergreen_irq_set: hdmi 2\n");
-   afmt3 |= AFMT_AZ_FORMAT_WTRIG_MASK;
-   }
-   if (rdev->irq.afmt[3]) {
-   DRM_DEBUG("evergreen_irq_set: hdmi 3\n");
-   afmt4 |= AFMT_AZ_FORMAT_WTRIG_MASK;
-   }
-   if (rdev->irq.afmt[4]) {
-   DRM_DEBUG("evergreen_irq_set: hdmi 4\n");
-   afmt5 |= AFMT_AZ_FORMAT_WTRIG_MASK;
-   }
-   if (rdev->irq.afmt[5]) {
-   DRM_DEBUG("evergreen_irq_set: hdmi 5\n");
-   afmt6 |= AFMT_AZ_FORMAT_WTRIG_MASK;
-   }
-
if (rdev->family >= CHIP_CAYMAN) {
cayman_cp_int_cntl_setup(rdev, 0, cp_int_cntl);
cayman_cp_int_cntl_setup(rdev, 1, cp_int_cntl1);
@@ -4643,12 +4610,12 @@ int evergreen_irq_set(struct radeon_device *rdev)
else
WREG32(CG_THERMAL_INT, thermal_int);
 
-   WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 
afmt1);
-   WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 
afmt2);
-   WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 
afmt3);
-   WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 
afmt4);
-   WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 
afmt5);
-   WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 
afmt6);
+   for (i = 0; i < 6; i++) {
+   radeon_irq_kms_set_irq_n_enabled(
+   rdev, AFMT_AUDIO_PACKET_CONTROL + crtc_offsets[i],
+   AFMT_AZ_FORMAT_WTRIG_MASK,
+   rdev->irq.afmt[i], "HDMI", i);
+   }
 
/* posting read */
RREG32(SRBM_STATUS);
@@ -4661,10 +4628,12 @@ static void evergreen_irq_ack(struct radeon_device 
*rdev)
 {
int i;
u32 *disp_int = rdev->irq.stat_regs.evergreen.disp_int;
-   u32 tmp;
+   u32 *afmt_status = rdev->irq.stat_regs.evergreen.afmt_status;
 
-   for (i = 0; i < 6; i++)
+   for (i = 0; i < 6; i++) {
disp_int[i] = RREG32(evergreen_disp_int_status[i]);
+   afmt_status[i] = RREG32(AFMT_STATUS + crtc_offsets[i]);
+   }
 
rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + 
EVERGREEN_CRTC0_REGISTER_OFFSET);
rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + 
EVERGREEN_CRTC1_REGISTER_OFFSET);
@@ -4677,12 +4646,6 @@ static void evergreen_irq_ack(struct radeon_device *rdev)
rdev->irq.stat_regs.evergreen.d6grph_int =

[PATCH v2 2/3] drm/radeon: Cleanup HDMI audio interrupt handling for evergreen

2017-05-19 Thread Lyude 
Same as the previous patch, but now for handling HDMI audio interrupts.

Changes since v1:
- Preserve the order we write back all registers

Signed-off-by: Lyude 
---
 drivers/gpu/drm/radeon/evergreen.c | 153 +++--
 drivers/gpu/drm/radeon/radeon.h|   7 +-
 2 files changed, 27 insertions(+), 133 deletions(-)

diff --git a/drivers/gpu/drm/radeon/evergreen.c 
b/drivers/gpu/drm/radeon/evergreen.c
index 44ac6d3..507a773 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -4495,7 +4495,6 @@ int evergreen_irq_set(struct radeon_device *rdev)
u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
u32 cp_int_cntl1 = 0, cp_int_cntl2 = 0;
u32 grbm_int_cntl = 0;
-   u32 afmt1 = 0, afmt2 = 0, afmt3 = 0, afmt4 = 0, afmt5 = 0, afmt6 = 0;
u32 dma_cntl, dma_cntl1 = 0;
u32 thermal_int = 0;
 
@@ -4518,13 +4517,6 @@ int evergreen_irq_set(struct radeon_device *rdev)
thermal_int = RREG32(CG_THERMAL_INT) &
~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
 
-   afmt1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + 
EVERGREEN_CRTC0_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
-   afmt2 = RREG32(AFMT_AUDIO_PACKET_CONTROL + 
EVERGREEN_CRTC1_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
-   afmt3 = RREG32(AFMT_AUDIO_PACKET_CONTROL + 
EVERGREEN_CRTC2_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
-   afmt4 = RREG32(AFMT_AUDIO_PACKET_CONTROL + 
EVERGREEN_CRTC3_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
-   afmt5 = RREG32(AFMT_AUDIO_PACKET_CONTROL + 
EVERGREEN_CRTC4_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
-   afmt6 = RREG32(AFMT_AUDIO_PACKET_CONTROL + 
EVERGREEN_CRTC5_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
-
dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
 
if (rdev->family >= CHIP_CAYMAN) {
@@ -4567,31 +4559,6 @@ int evergreen_irq_set(struct radeon_device *rdev)
thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
}
 
-   if (rdev->irq.afmt[0]) {
-   DRM_DEBUG("evergreen_irq_set: hdmi 0\n");
-   afmt1 |= AFMT_AZ_FORMAT_WTRIG_MASK;
-   }
-   if (rdev->irq.afmt[1]) {
-   DRM_DEBUG("evergreen_irq_set: hdmi 1\n");
-   afmt2 |= AFMT_AZ_FORMAT_WTRIG_MASK;
-   }
-   if (rdev->irq.afmt[2]) {
-   DRM_DEBUG("evergreen_irq_set: hdmi 2\n");
-   afmt3 |= AFMT_AZ_FORMAT_WTRIG_MASK;
-   }
-   if (rdev->irq.afmt[3]) {
-   DRM_DEBUG("evergreen_irq_set: hdmi 3\n");
-   afmt4 |= AFMT_AZ_FORMAT_WTRIG_MASK;
-   }
-   if (rdev->irq.afmt[4]) {
-   DRM_DEBUG("evergreen_irq_set: hdmi 4\n");
-   afmt5 |= AFMT_AZ_FORMAT_WTRIG_MASK;
-   }
-   if (rdev->irq.afmt[5]) {
-   DRM_DEBUG("evergreen_irq_set: hdmi 5\n");
-   afmt6 |= AFMT_AZ_FORMAT_WTRIG_MASK;
-   }
-
if (rdev->family >= CHIP_CAYMAN) {
cayman_cp_int_cntl_setup(rdev, 0, cp_int_cntl);
cayman_cp_int_cntl_setup(rdev, 1, cp_int_cntl1);
@@ -4643,12 +4610,12 @@ int evergreen_irq_set(struct radeon_device *rdev)
else
WREG32(CG_THERMAL_INT, thermal_int);
 
-   WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 
afmt1);
-   WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 
afmt2);
-   WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 
afmt3);
-   WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 
afmt4);
-   WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 
afmt5);
-   WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 
afmt6);
+   for (i = 0; i < 6; i++) {
+   radeon_irq_kms_set_irq_n_enabled(
+   rdev, AFMT_AUDIO_PACKET_CONTROL + crtc_offsets[i],
+   AFMT_AZ_FORMAT_WTRIG_MASK,
+   rdev->irq.afmt[i], "HDMI", i);
+   }
 
/* posting read */
RREG32(SRBM_STATUS);
@@ -4661,10 +4628,12 @@ static void evergreen_irq_ack(struct radeon_device 
*rdev)
 {
int i;
u32 *disp_int = rdev->irq.stat_regs.evergreen.disp_int;
-   u32 tmp;
+   u32 *afmt_status = rdev->irq.stat_regs.evergreen.afmt_status;
 
-   for (i = 0; i < 6; i++)
+   for (i = 0; i < 6; i++) {
disp_int[i] = RREG32(evergreen_disp_int_status[i]);
+   afmt_status[i] = RREG32(AFMT_STATUS + crtc_offsets[i]);
+   }
 
rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + 
EVERGREEN_CRTC0_REGISTER_OFFSET);
rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + 
EVERGREEN_CRTC1_REGISTER_OFFSET);
@@ -4677,12 +4646,6 @@ static void evergreen_irq_ack(struct radeon_device *rdev)
rdev->irq.stat_regs.evergreen.d6grph_int = 
RREG32(GRPH_INT_STATUS +