RE: [PATCH v2 2/3] soc: sifive: Add SiFive specific Cadence DDR controller driver

2020-09-17 Thread Dhananjay Vilasrao Kangude
.l...@intel.com; devicet...@vger.kernel.org; a...@eecs.berkeley.edu; > linux-kernel@vger.kernel.org; sachin.gh...@sifive.com; > rrich...@marvell.com; james.mo...@arm.com; linux- > ri...@lists.infradead.org; linux-e...@vger.kernel.org > Subject: Re: [PATCH v2 2/3] soc: sifive: Add SiFive spec

Re: [PATCH v2 2/3] soc: sifive: Add SiFive specific Cadence DDR controller driver

2020-09-09 Thread Palmer Dabbelt
On Tue, 08 Sep 2020 23:00:45 PDT (-0700), Christoph Hellwig wrote: On Tue, Sep 08, 2020 at 08:12:16PM -0700, Palmer Dabbelt wrote: I don't know enough about the block to know if the subtle difference in register names/offsets means. They look properly jumbled up (ie, not just an offset), so

Re: [PATCH v2 2/3] soc: sifive: Add SiFive specific Cadence DDR controller driver

2020-09-09 Thread Christoph Hellwig
On Tue, Sep 08, 2020 at 08:12:16PM -0700, Palmer Dabbelt wrote: > I don't know enough about the block to know if the subtle difference in > register names/offsets means. They look properly jumbled up (ie, not just an > offset), so maybe there's just different versions or that's the >

RE: [PATCH v2 2/3] soc: sifive: Add SiFive specific Cadence DDR controller driver

2020-09-08 Thread Yash Shah
et...@vger.kernel.org; > a...@eecs.berkeley.edu; linux-kernel@vger.kernel.org; Sachin Ghadi > ; rrich...@marvell.com; > james.mo...@arm.com; linux-ri...@lists.infradead.org; linux- > e...@vger.kernel.org > Subject: Re: [PATCH v2 2/3] soc: sifive: Add SiFive specific Cadence DDR > controller dr

Re: [PATCH v2 2/3] soc: sifive: Add SiFive specific Cadence DDR controller driver

2020-09-08 Thread Palmer Dabbelt
On Sun, 06 Sep 2020 23:11:26 PDT (-0700), Christoph Hellwig wrote: On Mon, Sep 07, 2020 at 11:17:58AM +0530, Yash Shah wrote: Add a driver to manage the Cadence DDR controller present on SiFive SoCs At present the driver manages the EDAC feature of the DDR controller. Additional features may be

Re: [PATCH v2 2/3] soc: sifive: Add SiFive specific Cadence DDR controller driver

2020-09-07 Thread Christoph Hellwig
On Mon, Sep 07, 2020 at 11:17:58AM +0530, Yash Shah wrote: > Add a driver to manage the Cadence DDR controller present on SiFive SoCs > At present the driver manages the EDAC feature of the DDR controller. > Additional features may be added to the driver in future to control > other aspects of the

Re: [PATCH v2 2/3] soc: sifive: Add SiFive specific Cadence DDR controller driver

2020-09-06 Thread Randy Dunlap
On 9/6/20 10:47 PM, Yash Shah wrote: > diff --git a/drivers/soc/sifive/Kconfig b/drivers/soc/sifive/Kconfig > index 58cf8c4..f41d8fe 100644 > --- a/drivers/soc/sifive/Kconfig > +++ b/drivers/soc/sifive/Kconfig > @@ -7,4 +7,10 @@ config SIFIVE_L2 > help > Support for the L2 cache

[PATCH v2 2/3] soc: sifive: Add SiFive specific Cadence DDR controller driver

2020-09-06 Thread Yash Shah
Add a driver to manage the Cadence DDR controller present on SiFive SoCs At present the driver manages the EDAC feature of the DDR controller. Additional features may be added to the driver in future to control other aspects of the DDR controller. Signed-off-by: Yash Shah Reviewed-by: Palmer