.l...@intel.com; devicet...@vger.kernel.org; a...@eecs.berkeley.edu;
> linux-kernel@vger.kernel.org; sachin.gh...@sifive.com;
> rrich...@marvell.com; james.mo...@arm.com; linux-
> ri...@lists.infradead.org; linux-e...@vger.kernel.org
> Subject: Re: [PATCH v2 2/3] soc: sifive: Add SiFive spec
On Tue, 08 Sep 2020 23:00:45 PDT (-0700), Christoph Hellwig wrote:
On Tue, Sep 08, 2020 at 08:12:16PM -0700, Palmer Dabbelt wrote:
I don't know enough about the block to know if the subtle difference in
register names/offsets means. They look properly jumbled up (ie, not just an
offset), so
On Tue, Sep 08, 2020 at 08:12:16PM -0700, Palmer Dabbelt wrote:
> I don't know enough about the block to know if the subtle difference in
> register names/offsets means. They look properly jumbled up (ie, not just an
> offset), so maybe there's just different versions or that's the
>
et...@vger.kernel.org;
> a...@eecs.berkeley.edu; linux-kernel@vger.kernel.org; Sachin Ghadi
> ; rrich...@marvell.com;
> james.mo...@arm.com; linux-ri...@lists.infradead.org; linux-
> e...@vger.kernel.org
> Subject: Re: [PATCH v2 2/3] soc: sifive: Add SiFive specific Cadence DDR
> controller dr
On Sun, 06 Sep 2020 23:11:26 PDT (-0700), Christoph Hellwig wrote:
On Mon, Sep 07, 2020 at 11:17:58AM +0530, Yash Shah wrote:
Add a driver to manage the Cadence DDR controller present on SiFive SoCs
At present the driver manages the EDAC feature of the DDR controller.
Additional features may be
On Mon, Sep 07, 2020 at 11:17:58AM +0530, Yash Shah wrote:
> Add a driver to manage the Cadence DDR controller present on SiFive SoCs
> At present the driver manages the EDAC feature of the DDR controller.
> Additional features may be added to the driver in future to control
> other aspects of the
On 9/6/20 10:47 PM, Yash Shah wrote:
> diff --git a/drivers/soc/sifive/Kconfig b/drivers/soc/sifive/Kconfig
> index 58cf8c4..f41d8fe 100644
> --- a/drivers/soc/sifive/Kconfig
> +++ b/drivers/soc/sifive/Kconfig
> @@ -7,4 +7,10 @@ config SIFIVE_L2
> help
> Support for the L2 cache
Add a driver to manage the Cadence DDR controller present on SiFive SoCs
At present the driver manages the EDAC feature of the DDR controller.
Additional features may be added to the driver in future to control
other aspects of the DDR controller.
Signed-off-by: Yash Shah
Reviewed-by: Palmer
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