Hi Jerome,
On 2018/12/13 17:04, Jerome Brunet wrote:
On Thu, 2018-12-13 at 16:39 +0800, Sunny Luo wrote:
The SPICC controller in Meson-AXG is capable of driving the CLK/MOSI/SS
signal lines through the idle state (between two transmission operation),
which avoid the signals floating in
Hi Neil,
On 2018/12/13 16:53, Neil Armstrong wrote:
Hi Sunny,
On 13/12/2018 09:39, Sunny Luo wrote:
The SPICC controller in Meson-AXG is capable of driving the CLK/MOSI/SS
signal lines through the idle state (between two transmission operation),
which avoid the signals floating in unexpected
Hi Mark,
On 2018/12/13 19:53, Mark Brown wrote:
On Thu, Dec 13, 2018 at 10:04:56AM +0100, Jerome Brunet wrote:
On Thu, 2018-12-13 at 16:39 +0800, Sunny Luo wrote:
writel_bits_relaxed(BIT(24), BIT(24), spicc->base + SPICC_TESTREG);
+ meson_spicc_oen_enable(spicc);
+
Any specific
On Thu, Dec 13, 2018 at 10:04:56AM +0100, Jerome Brunet wrote:
> On Thu, 2018-12-13 at 16:39 +0800, Sunny Luo wrote:
> >
> > writel_bits_relaxed(BIT(24), BIT(24), spicc->base + SPICC_TESTREG);
> >
> > + meson_spicc_oen_enable(spicc);
> > +
> Any specific reason for doing this in
On Thu, 2018-12-13 at 16:39 +0800, Sunny Luo wrote:
> The SPICC controller in Meson-AXG is capable of driving the CLK/MOSI/SS
> signal lines through the idle state (between two transmission operation),
> which avoid the signals floating in unexpected state.
>
> Signed-off-by: Sunny Luo
>
Hi Sunny,
On 13/12/2018 09:39, Sunny Luo wrote:
> The SPICC controller in Meson-AXG is capable of driving the CLK/MOSI/SS
> signal lines through the idle state (between two transmission operation),
> which avoid the signals floating in unexpected state.
This is welcome, because it's really
The SPICC controller in Meson-AXG is capable of driving the CLK/MOSI/SS
signal lines through the idle state (between two transmission operation),
which avoid the signals floating in unexpected state.
Signed-off-by: Sunny Luo
Signed-off-by: Yixun Lan
---
drivers/spi/spi-meson-spicc.c | 28
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