On Tue, Sep 15, 2020 at 11:07:55AM -0700, Moritz Fischer wrote:
> Hi Hao, Xu,
>
> On Tue, Sep 15, 2020 at 05:58:46AM +, Wu, Hao wrote:
> > > On Tue, Sep 15, 2020 at 12:08:38PM +0800, Wu, Hao wrote:
> > > > > On Tue, Sep 15, 2020 at 11:27:51AM +0800, Xu Yilun wrote:
> > > > > > Device Feature
Hi Hao, Xu,
On Tue, Sep 15, 2020 at 05:58:46AM +, Wu, Hao wrote:
> > On Tue, Sep 15, 2020 at 12:08:38PM +0800, Wu, Hao wrote:
> > > > On Tue, Sep 15, 2020 at 11:27:51AM +0800, Xu Yilun wrote:
> > > > > Device Feature List (DFL) is a linked list of feature headers within
> > > > > the
> > > >
On Tue, Sep 15, 2020 at 12:08:38PM +0800, Wu, Hao wrote:
> > On Tue, Sep 15, 2020 at 11:27:51AM +0800, Xu Yilun wrote:
> > > Device Feature List (DFL) is a linked list of feature headers within the
> > > device MMIO space. It is used by FPGA to enumerate multiple sub features
> > > within it. Each
On Tue, Sep 15, 2020 at 11:27:51AM +0800, Xu Yilun wrote:
> Device Feature List (DFL) is a linked list of feature headers within the
> device MMIO space. It is used by FPGA to enumerate multiple sub features
> within it. Each feature can be uniquely identified by DFL type and
> feature id, which
Device Feature List (DFL) is a linked list of feature headers within the
device MMIO space. It is used by FPGA to enumerate multiple sub features
within it. Each feature can be uniquely identified by DFL type and
feature id, which can be read out from feature headers.
A dfl bus helps DFL
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