[PATCH v2 3/4] rtc: ds1307: add offset sysfs for mt41txx chips.

2018-05-09 Thread Giulio Benetti
m41txx chips can hold a calibration value to get correct clock bias. If positive offset is passed, it means adding 512 cycles(@32.768Hz) every tick(1s). If negative offset is passed, it means subtracting 256 cycles(@32.768Hz) every tick(1s). Add offset handling (ranging between (-31) and 31) via

[PATCH v2 3/4] rtc: ds1307: add offset sysfs for mt41txx chips.

2018-05-09 Thread Giulio Benetti
m41txx chips can hold a calibration value to get correct clock bias. If positive offset is passed, it means adding 512 cycles(@32.768Hz) every tick(1s). If negative offset is passed, it means subtracting 256 cycles(@32.768Hz) every tick(1s). Add offset handling (ranging between (-31) and 31) via