On 7/23/2018 8:01 PM, Alex G. wrote:
On 07/23/2018 12:21 AM, Tal Gilboa wrote:
On 7/19/2018 6:49 PM, Alex G. wrote:
On 07/18/2018 08:38 AM, Tal Gilboa wrote:
On 7/16/2018 5:17 PM, Bjorn Helgaas wrote:
[+cc maintainers of drivers that already use pcie_print_link_status()
and GPU folks]
On 7/23/2018 8:01 PM, Alex G. wrote:
On 07/23/2018 12:21 AM, Tal Gilboa wrote:
On 7/19/2018 6:49 PM, Alex G. wrote:
On 07/18/2018 08:38 AM, Tal Gilboa wrote:
On 7/16/2018 5:17 PM, Bjorn Helgaas wrote:
[+cc maintainers of drivers that already use pcie_print_link_status()
and GPU folks]
On 07/23/2018 12:21 AM, Tal Gilboa wrote:
On 7/19/2018 6:49 PM, Alex G. wrote:
On 07/18/2018 08:38 AM, Tal Gilboa wrote:
On 7/16/2018 5:17 PM, Bjorn Helgaas wrote:
[+cc maintainers of drivers that already use pcie_print_link_status()
and GPU folks]
[snip]
+ /* Multi-function PCIe
On 07/23/2018 12:21 AM, Tal Gilboa wrote:
On 7/19/2018 6:49 PM, Alex G. wrote:
On 07/18/2018 08:38 AM, Tal Gilboa wrote:
On 7/16/2018 5:17 PM, Bjorn Helgaas wrote:
[+cc maintainers of drivers that already use pcie_print_link_status()
and GPU folks]
[snip]
+ /* Multi-function PCIe
On 7/19/2018 6:49 PM, Alex G. wrote:
On 07/18/2018 08:38 AM, Tal Gilboa wrote:
On 7/16/2018 5:17 PM, Bjorn Helgaas wrote:
[+cc maintainers of drivers that already use pcie_print_link_status()
and GPU folks]
[snip]
+ /* Multi-function PCIe share the same link/status. */
+ if
On 7/19/2018 6:49 PM, Alex G. wrote:
On 07/18/2018 08:38 AM, Tal Gilboa wrote:
On 7/16/2018 5:17 PM, Bjorn Helgaas wrote:
[+cc maintainers of drivers that already use pcie_print_link_status()
and GPU folks]
[snip]
+ /* Multi-function PCIe share the same link/status. */
+ if
On 07/18/2018 08:38 AM, Tal Gilboa wrote:
On 7/16/2018 5:17 PM, Bjorn Helgaas wrote:
[+cc maintainers of drivers that already use pcie_print_link_status()
and GPU folks]
[snip]
+ /* Multi-function PCIe share the same link/status. */
+ if ((PCI_FUNC(dev->devfn) != 0) ||
On 07/18/2018 08:38 AM, Tal Gilboa wrote:
On 7/16/2018 5:17 PM, Bjorn Helgaas wrote:
[+cc maintainers of drivers that already use pcie_print_link_status()
and GPU folks]
[snip]
+ /* Multi-function PCIe share the same link/status. */
+ if ((PCI_FUNC(dev->devfn) != 0) ||
On 07/18/2018 04:53 PM, Bjorn Helgaas wrote:
[+cc Mike (hfi1)]
On Mon, Jul 16, 2018 at 10:28:35PM +, alex_gagn...@dellteam.com wrote:
On 7/16/2018 4:17 PM, Bjorn Helgaas wrote:
...
The easiest way to detect this is with pcie_print_link_status(),
since the bottleneck is usually the link
On 07/18/2018 04:53 PM, Bjorn Helgaas wrote:
[+cc Mike (hfi1)]
On Mon, Jul 16, 2018 at 10:28:35PM +, alex_gagn...@dellteam.com wrote:
On 7/16/2018 4:17 PM, Bjorn Helgaas wrote:
...
The easiest way to detect this is with pcie_print_link_status(),
since the bottleneck is usually the link
[+cc Mike (hfi1)]
On Mon, Jul 16, 2018 at 10:28:35PM +, alex_gagn...@dellteam.com wrote:
> On 7/16/2018 4:17 PM, Bjorn Helgaas wrote:
> >> ...
> >> The easiest way to detect this is with pcie_print_link_status(),
> >> since the bottleneck is usually the link that is downtrained. It's not
> >>
[+cc Mike (hfi1)]
On Mon, Jul 16, 2018 at 10:28:35PM +, alex_gagn...@dellteam.com wrote:
> On 7/16/2018 4:17 PM, Bjorn Helgaas wrote:
> >> ...
> >> The easiest way to detect this is with pcie_print_link_status(),
> >> since the bottleneck is usually the link that is downtrained. It's not
> >>
On 7/16/2018 5:17 PM, Bjorn Helgaas wrote:
[+cc maintainers of drivers that already use pcie_print_link_status()
and GPU folks]
On Mon, Jun 04, 2018 at 10:55:21AM -0500, Alexandru Gagniuc wrote:
PCIe downtraining happens when both the device and PCIe port are
capable of a larger bus width or
On 7/16/2018 5:17 PM, Bjorn Helgaas wrote:
[+cc maintainers of drivers that already use pcie_print_link_status()
and GPU folks]
On Mon, Jun 04, 2018 at 10:55:21AM -0500, Alexandru Gagniuc wrote:
PCIe downtraining happens when both the device and PCIe port are
capable of a larger bus width or
On 7/16/2018 4:17 PM, Bjorn Helgaas wrote:
> [+cc maintainers of drivers that already use pcie_print_link_status()
> and GPU folks]
Thanks for finding them!
[snip]
>> identifying this from userspace is neither intuitive, nor straigh
>> forward.
>
> s/straigh/straight/
> In this context, I think
On 7/16/2018 4:17 PM, Bjorn Helgaas wrote:
> [+cc maintainers of drivers that already use pcie_print_link_status()
> and GPU folks]
Thanks for finding them!
[snip]
>> identifying this from userspace is neither intuitive, nor straigh
>> forward.
>
> s/straigh/straight/
> In this context, I think
[+cc maintainers of drivers that already use pcie_print_link_status()
and GPU folks]
On Mon, Jun 04, 2018 at 10:55:21AM -0500, Alexandru Gagniuc wrote:
> PCIe downtraining happens when both the device and PCIe port are
> capable of a larger bus width or higher speed than negotiated.
>
[+cc maintainers of drivers that already use pcie_print_link_status()
and GPU folks]
On Mon, Jun 04, 2018 at 10:55:21AM -0500, Alexandru Gagniuc wrote:
> PCIe downtraining happens when both the device and PCIe port are
> capable of a larger bus width or higher speed than negotiated.
>
On Tue, Jun 5, 2018 at 3:27 PM, Andy Shevchenko
wrote:
> On Mon, Jun 4, 2018 at 6:55 PM, Alexandru Gagniuc
> wrote:
>> PCIe downtraining happens when both the device and PCIe port are
>> capable of a larger bus width or higher speed than negotiated.
>> Downtraining might be indicative of other
On Tue, Jun 5, 2018 at 3:27 PM, Andy Shevchenko
wrote:
> On Mon, Jun 4, 2018 at 6:55 PM, Alexandru Gagniuc
> wrote:
>> PCIe downtraining happens when both the device and PCIe port are
>> capable of a larger bus width or higher speed than negotiated.
>> Downtraining might be indicative of other
On Mon, Jun 4, 2018 at 6:55 PM, Alexandru Gagniuc wrote:
> PCIe downtraining happens when both the device and PCIe port are
> capable of a larger bus width or higher speed than negotiated.
> Downtraining might be indicative of other problems in the system, and
> identifying this from userspace is
On Mon, Jun 4, 2018 at 6:55 PM, Alexandru Gagniuc wrote:
> PCIe downtraining happens when both the device and PCIe port are
> capable of a larger bus width or higher speed than negotiated.
> Downtraining might be indicative of other problems in the system, and
> identifying this from userspace is
PCIe downtraining happens when both the device and PCIe port are
capable of a larger bus width or higher speed than negotiated.
Downtraining might be indicative of other problems in the system, and
identifying this from userspace is neither intuitive, nor straigh
forward.
The easiest way to
PCIe downtraining happens when both the device and PCIe port are
capable of a larger bus width or higher speed than negotiated.
Downtraining might be indicative of other problems in the system, and
identifying this from userspace is neither intuitive, nor straigh
forward.
The easiest way to
24 matches
Mail list logo
