On Wed, Mar 11, 2015 at 03:44:39PM +, Sudeep Holla wrote:
> It looks fine to me except one unwanted/incorrect line in the commit log as
> mentioned below. I gave it a spin on my i7 box and it works.
> Thanks for the fix up.
Thanks for testing.
> After testing this patch, I think I had
Hi Boris,
On 11/03/15 13:36, Borislav Petkov wrote:
On Tue, Mar 10, 2015 at 02:35:12PM +, Sudeep Holla wrote:
My initial assumption was that it will be NULL for Intel processors
and hence I assigned cacheinfo->priv to nb pointer unconditionally. So
I don't have any strong opinion here.
On Tue, Mar 10, 2015 at 02:35:12PM +, Sudeep Holla wrote:
> My initial assumption was that it will be NULL for Intel processors
> and hence I assigned cacheinfo->priv to nb pointer unconditionally. So
> I don't have any strong opinion here.
Right, we need the NB descriptor on AMD to do
Hi Boris,
On 11/03/15 13:36, Borislav Petkov wrote:
On Tue, Mar 10, 2015 at 02:35:12PM +, Sudeep Holla wrote:
My initial assumption was that it will be NULL for Intel processors
and hence I assigned cacheinfo-priv to nb pointer unconditionally. So
I don't have any strong opinion here.
On Wed, Mar 11, 2015 at 03:44:39PM +, Sudeep Holla wrote:
It looks fine to me except one unwanted/incorrect line in the commit log as
mentioned below. I gave it a spin on my i7 box and it works.
Thanks for the fix up.
Thanks for testing.
After testing this patch, I think I had
On Tue, Mar 10, 2015 at 02:35:12PM +, Sudeep Holla wrote:
My initial assumption was that it will be NULL for Intel processors
and hence I assigned cacheinfo-priv to nb pointer unconditionally. So
I don't have any strong opinion here.
Right, we need the NB descriptor on AMD to do
On 10/03/15 14:26, Borislav Petkov wrote:
On Tue, Mar 10, 2015 at 02:22:22PM +, Sudeep Holla wrote:
I was able to reproduce this and now I realise I had CONFIG_AMD_NB
disabled in my config earlier which hid this issue previously, sorry
for that.
The below patch fixed the issue on my
On Tue, Mar 10, 2015 at 02:22:22PM +, Sudeep Holla wrote:
> I was able to reproduce this and now I realise I had CONFIG_AMD_NB
> disabled in my config earlier which hid this issue previously, sorry
> for that.
>
> The below patch fixed the issue on my Intel i7 box. I can post this
>
On Tue, Mar 10, 2015 at 11:53:35AM +, Sudeep Holla wrote:
Hi Boris,
On 10/03/15 11:37, Borislav Petkov wrote:
> Hi,
>
> I just triggered this is on rc3 + tip/master which has your patch. This
> is an Intel SNB. Ideas, already fixed?
>
No, not seen this before. I will test tip/master on my
Hi Boris,
On 10/03/15 11:37, Borislav Petkov wrote:
Hi,
I just triggered this is on rc3 + tip/master which has your patch. This
is an Intel SNB. Ideas, already fixed?
No, not seen this before. I will test tip/master on my Intel i7 box
again and get back to you.
Regards,
Sudeep
--
To
Hi,
I just triggered this is on rc3 + tip/master which has your patch. This
is an Intel SNB. Ideas, already fixed?
Thanks.
[ cut here ]
WARNING: CPU: 3 PID: 1 at fs/sysfs/group.c:102
internal_create_group+0x151/0x280()
sysfs: (bin_)attrs not set by subsystem for group:
Hi Boris,
On 10/03/15 11:37, Borislav Petkov wrote:
Hi,
I just triggered this is on rc3 + tip/master which has your patch. This
is an Intel SNB. Ideas, already fixed?
No, not seen this before. I will test tip/master on my Intel i7 box
again and get back to you.
Regards,
Sudeep
--
To
Hi,
I just triggered this is on rc3 + tip/master which has your patch. This
is an Intel SNB. Ideas, already fixed?
Thanks.
[ cut here ]
WARNING: CPU: 3 PID: 1 at fs/sysfs/group.c:102
internal_create_group+0x151/0x280()
sysfs: (bin_)attrs not set by subsystem for group:
On Tue, Mar 10, 2015 at 11:53:35AM +, Sudeep Holla wrote:
Hi Boris,
On 10/03/15 11:37, Borislav Petkov wrote:
Hi,
I just triggered this is on rc3 + tip/master which has your patch. This
is an Intel SNB. Ideas, already fixed?
No, not seen this before. I will test tip/master on my Intel
On Tue, Mar 10, 2015 at 02:22:22PM +, Sudeep Holla wrote:
I was able to reproduce this and now I realise I had CONFIG_AMD_NB
disabled in my config earlier which hid this issue previously, sorry
for that.
The below patch fixed the issue on my Intel i7 box. I can post this
separately if
On 10/03/15 14:26, Borislav Petkov wrote:
On Tue, Mar 10, 2015 at 02:22:22PM +, Sudeep Holla wrote:
I was able to reproduce this and now I realise I had CONFIG_AMD_NB
disabled in my config earlier which hid this issue previously, sorry
for that.
The below patch fixed the issue on my
Hi Boris,
On 05/03/15 08:16, Borislav Petkov wrote:
On Wed, Mar 04, 2015 at 01:27:20PM +0100, Borislav Petkov wrote:
Applied, thanks guys.
Ok, we forgot to add the same check in the cpu_has_topoext case in
__cache_amd_cpumap_setup() and my F15h exploded this morning:
---
diff --git
On Wed, Mar 04, 2015 at 01:27:20PM +0100, Borislav Petkov wrote:
> Applied, thanks guys.
Ok, we forgot to add the same check in the cpu_has_topoext case in
__cache_amd_cpumap_setup() and my F15h exploded this morning:
---
diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c
On Wed, Mar 04, 2015 at 01:27:20PM +0100, Borislav Petkov wrote:
Applied, thanks guys.
Ok, we forgot to add the same check in the cpu_has_topoext case in
__cache_amd_cpumap_setup() and my F15h exploded this morning:
---
diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c
Hi Boris,
On 05/03/15 08:16, Borislav Petkov wrote:
On Wed, Mar 04, 2015 at 01:27:20PM +0100, Borislav Petkov wrote:
Applied, thanks guys.
Ok, we forgot to add the same check in the cpu_has_topoext case in
__cache_amd_cpumap_setup() and my F15h exploded this morning:
---
diff --git
On Wed, Mar 04, 2015 at 12:00:16PM +, Sudeep Holla wrote:
> This patch removes the redundant sysfs cacheinfo code by reusing
> the newly introduced generic cacheinfo infrastructure through the
> commit 246246cbde5e ("drivers: base: support cpu cache information
> interface to userspace via
This patch removes the redundant sysfs cacheinfo code by reusing
the newly introduced generic cacheinfo infrastructure through the
commit 246246cbde5e ("drivers: base: support cpu cache information
interface to userspace via sysfs")
The private pointer provided by the cacheinfo is used to
This patch removes the redundant sysfs cacheinfo code by reusing
the newly introduced generic cacheinfo infrastructure through the
commit 246246cbde5e (drivers: base: support cpu cache information
interface to userspace via sysfs)
The private pointer provided by the cacheinfo is used to implement
On Wed, Mar 04, 2015 at 12:00:16PM +, Sudeep Holla wrote:
This patch removes the redundant sysfs cacheinfo code by reusing
the newly introduced generic cacheinfo infrastructure through the
commit 246246cbde5e (drivers: base: support cpu cache information
interface to userspace via sysfs)
24 matches
Mail list logo
