[PATCH v3 02/12] clk: samsung: exynos5433: Add MUX clocks of CMU_TOP domain
This patch adds the MUX (multiplexer) clocks for CMU_TOP domain of Exynos5433.
CMU_TOP domain provides source clocks to other CMU domains.
Cc: Sylwester Nawrocki
Cc: Tomasz Figa
Signed-off-by: Chanwoo Choi
Acked-by: Inki Dae
Reviewed-by: Pankaj Dubey
---
drivers/clk/samsung/clk-exynos5433.c | 90 ++
include/dt-bindings/clock/exynos5433.h | 31 +++-
2 files changed, 119 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5433.c
b/drivers/clk/samsung/clk-exynos5433.c
index 59a87bc..077fa61 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -208,6 +208,7 @@ PNAME(mout_mphy_pll_user_p) = { "fin_pll", "sclk_mphy_pll",
};
PNAME(mout_mfc_pll_user_p) = { "fin_pll", "sclk_mfc_pll", };
PNAME(mout_bus_pll_user_p) = { "fin_pll", "sclk_bus_pll", };
PNAME(mout_bus_pll_user_t_p) = { "fin_pll", "mout_bus_pll_user", };
+PNAME(mout_mphy_pll_user_t_p) = { "fin_pll", "mout_mphy_pll_user", };
PNAME(mout_bus_mfc_pll_user_p) = { "mout_bus_pll_user", "mout_mfc_pll_user",};
PNAME(mout_mfc_bus_pll_user_p) = { "mout_mfc_pll_user", "mout_bus_pll_user",};
@@ -215,6 +216,12 @@ PNAME(mout_aclk_cam1_552_b_p) = {
"mout_aclk_cam1_552_a",
"mout_mfc_pll_user", };
PNAME(mout_aclk_cam1_552_a_p) = { "mout_isp_pll", "mout_bus_pll_user", };
+PNAME(mout_aclk_mfc_400_c_p) = { "mout_aclk_mfc_400_b",
+ "mout_mphy_pll_user", };
+PNAME(mout_aclk_mfc_400_b_p) = { "mout_aclk_mfc_400_a",
+ "mout_bus_pll_user", };
+PNAME(mout_aclk_mfc_400_a_p) = { "mout_mfc_pll_user", "mout_isp_pll", };
+
PNAME(mout_bus_mphy_pll_user_p)= { "mout_bus_pll_user",
"mout_mphy_pll_user", };
PNAME(mout_aclk_mscl_b_p) = { "mout_aclk_mscl_400_a",
@@ -231,6 +238,21 @@ PNAME(mout_sclk_mmc0_d_p) = { "mout_sclk_mmc0_c",
"mout_isp_pll", };
PNAME(mout_sclk_mmc0_c_p) = { "mout_sclk_mmc0_b", "mout_mphy_pll_user",};
PNAME(mout_sclk_mmc0_b_p) = { "mout_sclk_mmc0_a", "mout_mfc_pll_user", };
+PNAME(mout_sclk_spdif_p) = { "sclk_audio0", "sclk_audio1",
+ "fin_pll", "ioclk_spdif_extclk", };
+PNAME(mout_sclk_audio1_p) = { "ioclk_audiocdclk1", "fin_pll",
+ "mout_aud_pll_user_t",};
+PNAME(mout_sclk_audio0_p) = { "ioclk_audiocdclk0", "fin_pll",
+ "mout_aud_pll_user_t",};
+
+static struct samsung_fixed_rate_clock top_fixed_clks[] __initdata = {
+ /* Xi2s{0|1}CDCLK input clock for I2S/PCM */
+ FRATE(0, "ioclk_audiocdclk1", NULL, CLK_IS_ROOT, 1),
+ FRATE(0, "ioclk_audiocdclk0", NULL, CLK_IS_ROOT, 1),
+ /* Xi2s1SDI input clock for SPDIF */
+ FRATE(0, "ioclk_spdif_extclk", NULL, CLK_IS_ROOT, 1),
+};
+
static struct samsung_mux_clock top_mux_clks[] __initdata = {
/* MUX_SEL_TOP0 */
MUX(CLK_MOUT_AUD_PLL, "mout_aud_pll", mout_aud_pll_p, MUX_SEL_TOP0,
@@ -276,6 +298,14 @@ static struct samsung_mux_clock top_mux_clks[] __initdata
= {
MUX(CLK_MOUT_ACLK_G2D_400_A, "mout_aclk_g2d_400_a",
mout_bus_mfc_pll_user_p, MUX_SEL_TOP3, 0, 1),
+ /* MUX_SEL_TOP4 */
+ MUX(CLK_MOUT_ACLK_MFC_400_C, "mout_aclk_mfc_400_c",
+ mout_aclk_mfc_400_c_p, MUX_SEL_TOP4, 8, 1),
+ MUX(CLK_MOUT_ACLK_MFC_400_B, "mout_aclk_mfc_400_b",
+ mout_aclk_mfc_400_b_p, MUX_SEL_TOP4, 4, 1),
+ MUX(CLK_MOUT_ACLK_MFC_400_A, "mout_aclk_mfc_400_a",
+ mout_aclk_mfc_400_a_p, MUX_SEL_TOP4, 0, 1),
+
/* MUX_SEL_TOP_MSCL */
MUX(CLK_MOUT_SCLK_JPEG_C, "mout_sclk_jpeg_c", mout_sclk_jpeg_c_p,
MUX_SEL_TOP_MSCL, 8, 1),
@@ -284,6 +314,20 @@ static struct samsung_mux_clock top_mux_clks[] __initdata
= {
MUX(CLK_MOUT_SCLK_JPEG_A, "mout_sclk_jpeg_a", mout_bus_pll_user_t_p,
MUX_SEL_TOP_MSCL, 0, 1),
+ /* MUX_SEL_TOP_CAM1 */
+ MUX(CLK_MOUT_SCLK_ISP_SENSOR2, "mout_sclk_isp_sensor2",
+ mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 24, 1),
+ MUX(CLK_MOUT_SCLK_ISP_SENSOR1, "mout_sclk_isp_sensor1",
+ mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 20, 1),
+ MUX(CLK_MOUT_SCLK_ISP_SENSOR0, "mout_sclk_isp_sensor0",
+ mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 16, 1),
+ MUX(CLK_MOUT_SCLK_ISP_UART, "mout_sclk_isp_uart",
+ mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 8, 1),
+ MUX(CLK_MOUT_SCLK_ISP_SPI1, "mout_sclk_isp_spi1",
+ mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 4, 1),
+ MUX(CLK_MOUT_SCLK_ISP_SPI0, "mout_sclk_isp_spi0",
+ mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 0, 1),
+
/* MUX_SEL_TOP_FSYS0 */
[PATCH v3 02/12] clk: samsung: exynos5433: Add MUX clocks of CMU_TOP domain
This patch adds the MUX (multiplexer) clocks for CMU_TOP domain of Exynos5433.
CMU_TOP domain provides source clocks to other CMU domains.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
Reviewed-by: Pankaj Dubey pankaj.du...@samsung.com
---
drivers/clk/samsung/clk-exynos5433.c | 90 ++
include/dt-bindings/clock/exynos5433.h | 31 +++-
2 files changed, 119 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5433.c
b/drivers/clk/samsung/clk-exynos5433.c
index 59a87bc..077fa61 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -208,6 +208,7 @@ PNAME(mout_mphy_pll_user_p) = { fin_pll, sclk_mphy_pll,
};
PNAME(mout_mfc_pll_user_p) = { fin_pll, sclk_mfc_pll, };
PNAME(mout_bus_pll_user_p) = { fin_pll, sclk_bus_pll, };
PNAME(mout_bus_pll_user_t_p) = { fin_pll, mout_bus_pll_user, };
+PNAME(mout_mphy_pll_user_t_p) = { fin_pll, mout_mphy_pll_user, };
PNAME(mout_bus_mfc_pll_user_p) = { mout_bus_pll_user, mout_mfc_pll_user,};
PNAME(mout_mfc_bus_pll_user_p) = { mout_mfc_pll_user, mout_bus_pll_user,};
@@ -215,6 +216,12 @@ PNAME(mout_aclk_cam1_552_b_p) = {
mout_aclk_cam1_552_a,
mout_mfc_pll_user, };
PNAME(mout_aclk_cam1_552_a_p) = { mout_isp_pll, mout_bus_pll_user, };
+PNAME(mout_aclk_mfc_400_c_p) = { mout_aclk_mfc_400_b,
+ mout_mphy_pll_user, };
+PNAME(mout_aclk_mfc_400_b_p) = { mout_aclk_mfc_400_a,
+ mout_bus_pll_user, };
+PNAME(mout_aclk_mfc_400_a_p) = { mout_mfc_pll_user, mout_isp_pll, };
+
PNAME(mout_bus_mphy_pll_user_p)= { mout_bus_pll_user,
mout_mphy_pll_user, };
PNAME(mout_aclk_mscl_b_p) = { mout_aclk_mscl_400_a,
@@ -231,6 +238,21 @@ PNAME(mout_sclk_mmc0_d_p) = { mout_sclk_mmc0_c,
mout_isp_pll, };
PNAME(mout_sclk_mmc0_c_p) = { mout_sclk_mmc0_b, mout_mphy_pll_user,};
PNAME(mout_sclk_mmc0_b_p) = { mout_sclk_mmc0_a, mout_mfc_pll_user, };
+PNAME(mout_sclk_spdif_p) = { sclk_audio0, sclk_audio1,
+ fin_pll, ioclk_spdif_extclk, };
+PNAME(mout_sclk_audio1_p) = { ioclk_audiocdclk1, fin_pll,
+ mout_aud_pll_user_t,};
+PNAME(mout_sclk_audio0_p) = { ioclk_audiocdclk0, fin_pll,
+ mout_aud_pll_user_t,};
+
+static struct samsung_fixed_rate_clock top_fixed_clks[] __initdata = {
+ /* Xi2s{0|1}CDCLK input clock for I2S/PCM */
+ FRATE(0, ioclk_audiocdclk1, NULL, CLK_IS_ROOT, 1),
+ FRATE(0, ioclk_audiocdclk0, NULL, CLK_IS_ROOT, 1),
+ /* Xi2s1SDI input clock for SPDIF */
+ FRATE(0, ioclk_spdif_extclk, NULL, CLK_IS_ROOT, 1),
+};
+
static struct samsung_mux_clock top_mux_clks[] __initdata = {
/* MUX_SEL_TOP0 */
MUX(CLK_MOUT_AUD_PLL, mout_aud_pll, mout_aud_pll_p, MUX_SEL_TOP0,
@@ -276,6 +298,14 @@ static struct samsung_mux_clock top_mux_clks[] __initdata
= {
MUX(CLK_MOUT_ACLK_G2D_400_A, mout_aclk_g2d_400_a,
mout_bus_mfc_pll_user_p, MUX_SEL_TOP3, 0, 1),
+ /* MUX_SEL_TOP4 */
+ MUX(CLK_MOUT_ACLK_MFC_400_C, mout_aclk_mfc_400_c,
+ mout_aclk_mfc_400_c_p, MUX_SEL_TOP4, 8, 1),
+ MUX(CLK_MOUT_ACLK_MFC_400_B, mout_aclk_mfc_400_b,
+ mout_aclk_mfc_400_b_p, MUX_SEL_TOP4, 4, 1),
+ MUX(CLK_MOUT_ACLK_MFC_400_A, mout_aclk_mfc_400_a,
+ mout_aclk_mfc_400_a_p, MUX_SEL_TOP4, 0, 1),
+
/* MUX_SEL_TOP_MSCL */
MUX(CLK_MOUT_SCLK_JPEG_C, mout_sclk_jpeg_c, mout_sclk_jpeg_c_p,
MUX_SEL_TOP_MSCL, 8, 1),
@@ -284,6 +314,20 @@ static struct samsung_mux_clock top_mux_clks[] __initdata
= {
MUX(CLK_MOUT_SCLK_JPEG_A, mout_sclk_jpeg_a, mout_bus_pll_user_t_p,
MUX_SEL_TOP_MSCL, 0, 1),
+ /* MUX_SEL_TOP_CAM1 */
+ MUX(CLK_MOUT_SCLK_ISP_SENSOR2, mout_sclk_isp_sensor2,
+ mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 24, 1),
+ MUX(CLK_MOUT_SCLK_ISP_SENSOR1, mout_sclk_isp_sensor1,
+ mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 20, 1),
+ MUX(CLK_MOUT_SCLK_ISP_SENSOR0, mout_sclk_isp_sensor0,
+ mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 16, 1),
+ MUX(CLK_MOUT_SCLK_ISP_UART, mout_sclk_isp_uart,
+ mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 8, 1),
+ MUX(CLK_MOUT_SCLK_ISP_SPI1, mout_sclk_isp_spi1,
+ mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 4, 1),
+ MUX(CLK_MOUT_SCLK_ISP_SPI0, mout_sclk_isp_spi0,
+ mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 0, 1),
+
/* MUX_SEL_TOP_FSYS0 */
MUX(CLK_MOUT_SCLK_MMC2_B,
