[PATCH v3 02/15] clk: tegra: Add library for the DFLL clock source (open-loop mode)

From: Tuomas Tynkkynen Add shared code to support the Tegra DFLL clocksource in open-loop mode. This root clocksource is present on the Tegra124 SoCs. The DFLL is the intended primary clock source for the fast CPU cluster. This code is very closely based on a patch by Paul Walmsley from

[PATCH v3 02/15] clk: tegra: Add library for the DFLL clock source (open-loop mode)

From: Tuomas Tynkkynen ttynkky...@nvidia.com Add shared code to support the Tegra DFLL clocksource in open-loop mode. This root clocksource is present on the Tegra124 SoCs. The DFLL is the intended primary clock source for the fast CPU cluster. This code is very closely based on a patch by Paul