It was added some extra checks to ensure that the driver doesn't try to
use more DMA channels than actually are available in hardware.

Signed-off-by: Gustavo Pimentel <gustavo.pimen...@synopsys.com>
---
 drivers/dma/dw-edma/dw-edma-core.c | 21 +++++++++------------
 drivers/dma/dw-edma/dw-edma-core.h |  2 ++
 2 files changed, 11 insertions(+), 12 deletions(-)

diff --git a/drivers/dma/dw-edma/dw-edma-core.c 
b/drivers/dma/dw-edma/dw-edma-core.c
index 0fe3835..5495cf7 100644
--- a/drivers/dma/dw-edma/dw-edma-core.c
+++ b/drivers/dma/dw-edma/dw-edma-core.c
@@ -914,19 +914,16 @@ int dw_edma_probe(struct dw_edma_chip *chip)
 
        raw_spin_lock_init(&dw->lock);
 
-       if (!dw->wr_ch_cnt) {
-               /* Find out how many write channels are supported by hardware */
-               dw->wr_ch_cnt = dw_edma_v0_core_ch_count(dw, EDMA_DIR_WRITE);
-               if (!dw->wr_ch_cnt)
-                       return -EINVAL;
-       }
+       dw->wr_ch_cnt = min_t(u16, dw->wr_ch_cnt,
+                             dw_edma_v0_core_ch_count(dw, EDMA_DIR_WRITE));
+       dw->wr_ch_cnt = min_t(u16, dw->wr_ch_cnt, EDMA_MAX_WR_CH);
 
-       if (!dw->rd_ch_cnt) {
-               /* Find out how many read channels are supported by hardware */
-               dw->rd_ch_cnt = dw_edma_v0_core_ch_count(dw, EDMA_DIR_READ);
-               if (!dw->rd_ch_cnt)
-                       return -EINVAL;
-       }
+       dw->rd_ch_cnt = min_t(u16, dw->rd_ch_cnt,
+                             dw_edma_v0_core_ch_count(dw, EDMA_DIR_READ));
+       dw->rd_ch_cnt = min_t(u16, dw->rd_ch_cnt, EDMA_MAX_RD_CH);
+
+       if (!dw->wr_ch_cnt && !dw->rd_ch_cnt)
+               return -EINVAL;
 
        dev_vdbg(dev, "Channels:\twrite=%d, read=%d\n",
                 dw->wr_ch_cnt, dw->rd_ch_cnt);
diff --git a/drivers/dma/dw-edma/dw-edma-core.h 
b/drivers/dma/dw-edma/dw-edma-core.h
index f72ebaa..650b1c7 100644
--- a/drivers/dma/dw-edma/dw-edma-core.h
+++ b/drivers/dma/dw-edma/dw-edma-core.h
@@ -15,6 +15,8 @@
 #include "../virt-dma.h"
 
 #define EDMA_LL_SZ                                     24
+#define EDMA_MAX_WR_CH                                 8
+#define EDMA_MAX_RD_CH                                 8
 
 enum dw_edma_dir {
        EDMA_DIR_WRITE = 0,
-- 
2.7.4

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